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Shrinath K Thelapurath

from Los Gatos, CA
Age ~49
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Also known as:
Shrinath Kutty Thelapurath, Thelapurath K Shrinath, Kult T Shinath, Shrinath H
Phone and address:
120 Carlton Ave UNIT 51, Los Gatos, CA 95032
Related to:
Alice ThomasPooja ShrinathPooja Shrinath, 46Madathil Dilip Kutty, 44Ranjit Menon, 50Deepthi K Madathil, 40Ka Menon
Connected to:
Lynnetta R Thele, 62June A Thelemaque, 58Kerri S Theleman, 52Shaenika G Thelemaque, 39Andrew J Thelen, 55Bryon C Thelen, 42Cherie A Thelen, 53Danielle Thelen, 30Denis M Thelen, 80Duane K Thelen, 59

Shrinath Thelapurath Phones & Addresses

  • 120 Carlton Ave UNIT 51, Los Gatos, CA 95032
  • Pleasanton, CA
  • Cupertino, CA
  • 212 Thelin Ct, Wilmette, IL 60091 (847) 728-0516
  • 26100 Canyon Creek Rd, Wilsonville, OR 97070 (503) 682-7951
  • 6939 Wilsonville Rd, Wilsonville, OR 97070 (503) 682-7951
  • Pittsburgh, PA
  • Tualatin, OR
  • Houston, TX

Publications

Us Patents

Extracting High Frequency Impedance In A Circuit Design Using An Electronic Design Automation Tool

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US Patent:
7689962, Mar 30, 2010
Filed:
Feb 8, 2007
Appl. No.:
11/704588
Inventors:
Roberto Suaya - 38240 Meylan, FR
Rafael Escovar - 38000 Grenoble, FR
Shrinath Thelapurath - Wilsonville OR, US
Salvador Ortiz - 38000 Grenoble, FR
Dusan Petranovic - Cupertino CA, US
International Classification:
G06F 17/50
US Classification:
716 10, 716 4
Abstract:
Exemplary impedance extraction methods, systems, and apparatus are described herein. In one exemplary embodiment, for instance, a signal-wire segment of a circuit layout is selected. A predetermined number of return paths are identified for the selected signal-wire segment. The selected signal-wire segment and the identified return paths are further segmented into a plurality of bundles, which comprise signal-wire subsegments and one or more associated return-path subsegments that are parallel to and have the same length as the signal-wire subsegments. Loop inductance values and loop resistance values are determined and stored for the signal-wire subsegments in the bundles for at least one frequency of operation. Computer-readable media storing computer-executable instructions for causing a computer to perform any of the disclosed methods or storing data or information created or modified using any of the disclosed techniques are also disclosed.

Extracting High Frequency Impedance In A Circuit Design Using Broadband Representations

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US Patent:
20070225925, Sep 27, 2007
Filed:
Feb 8, 2007
Appl. No.:
11/704470
Inventors:
Roberto Suaya - Meylan, FR
Rafael Escovar - Grenoble, FR
Shrinath Thelapurath - Wilsonville OR, US
Salvador Ortiz - Grenoble, FR
International Classification:
G06F 19/00
US Classification:
702057000, 702001000, 324600000
Abstract:
Exemplary impedance extraction methods, systems, and apparatus are described herein. In one exemplary embodiment, at least a portion of a circuit description indicative of a circuit layout is loaded. A signal-wire segment is selected. Loop inductance values and loop resistance values for the signal-wire segment are determined at at least a first frequency of operation and a second frequency of operation. Values for one or more inductance components and one or more resistance components of a broadband representation of the signal-wire segment are computed and stored. In this embodiment, the broadband representation comprises at least one but no more than two parallel-coupled resistance components and inductance components. Computer-readable media storing computer-executable instructions for causing a computer to perform any of the disclosed methods or storing data or information created or modified using any of the disclosed techniques are also disclosed.

Extracting High Frequency Impedance In A Circuit Design Using An Electronic Design Automation Tool

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US Patent:
20100251191, Sep 30, 2010
Filed:
Mar 29, 2010
Appl. No.:
12/749237
Inventors:
Roberto Suaya - Meylan, FR
Rafael Escovar - Grenoble, FR
Shrinath Thelapurath - Wilsonville OR, US
Salvador Ortiz - Grenoble, FR
Dusan Petranovic - Cupertino CA, US
International Classification:
G06F 17/50
US Classification:
716 4, 716 10
Abstract:
Exemplary impedance extraction methods, systems, and apparatus are described herein. In one exemplary embodiment, for instance, a signal-wire segment of a circuit layout is selected. A predetermined number of return paths are identified for the selected signal-wire segment. The selected signal-wire segment and the identified return paths are further segmented into a plurality of bundles, which comprise signal-wire subsegments and one or more associated return-path subsegments that are parallel to and have the same length as the signal-wire subsegments. Loop inductance values and loop resistance values are determined and stored for the signal-wire subsegments in the bundles for at least one frequency of operation. Computer-readable media storing computer-executable instructions for causing a computer to perform any of the disclosed methods or storing data or information created or modified using any of the disclosed techniques are also disclosed.
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Shrinath K Thelapurath from Los Gatos, CA, age ~49 Get Report