Shobhana R Punjabi

61717371, Jan 9, 2001

Feb 3, 1998

9/017695

Khoi A. Phan - San Jose CA
Shobhana R. Punjabi - San Jose CA
Robert J. Chiu - Mt. View CA
Bhanwar Singh - Morgan Hill CA

Advanced Micro Devices, Inc. - Sunnyvale CA

G03F 900

430 30

A low cost technique for detecting defects in photolithography processes in a submicron integrated circuit manufacturing environment combines use of a reusable test wafer with in-line processing to monitor defects using a pattern comparator system. A reusable test wafer having an oxide layer overlying a silicon substrate and having a thickness corresponding to a minimum reflectance for an exposure wavelength used for photolithography is patterned using a prescribed photolithographic fabrication process to form a repetitive pattern according to a prescribed design product rule. The pattern is formed using a reticle having a repetitive pattern array with a similar design rule as the product to be developed by the lithography processes. The patterned test wafer is then inspected using image-based inspection techniques, where the image has high resolution pixels of preferably 0. 25 microns per pixel.

20230071476, Mar 9, 2023

Mar 24, 2022

17/702892

- San Jose CA, US
Shobhana Ram Punjabi - San Jose CA, US
Jie Xue - Dublin CA, US

H01L 23/498

A multi-layer substrate stacking a plurality of insulating substrates supports one or more devices. Each substrate includes a face supporting conductive traces and edges surrounding the face at a substantially perpendicular angle. The multi-layer substrate includes a ground plane on a first substrate and a power plane on a second substrate. The ground plane is connected to at least one ground pad disposed on a first edge of the first substrate, which provides a low inductance ground path to the ground plane. The power plane is connected to at least one power pad disposed on a second edge of the second substrate, which provides a low inductance power path to the power plane.

20170229257, Aug 10, 2017

Apr 27, 2017

15/498999

- San Jose CA, US
Yang Li - San Jose CA, US
Jessica Leigh Kiefer - San Jose CA, US
Kan Chiu Seto - Saratoga CA, US
Shobhana Punjabi - San Jose CA, US

H01H 9/54

In one embodiment, a hot swap circuit is disclosed. The hot swap circuit includes a first switch connected to a power input line. The hot swap circuit also includes a first capacitor connected to the first switch that is charged when the first switch is closed. The hot swap circuit further includes a second switch connected to the first switch and the first capacitor. The hot swap circuit additionally includes an input capacitor connected to the second switch and located in parallel with an input line to a power system. When the second switch is closed, the input capacitor is charged.

20170045929, Feb 16, 2017

Aug 12, 2015

14/824282

- San Jose CA, US
Yang Li - San Jose CA, US
Jessica Leigh Kiefer - San Jose CA, US
Kan Chiu Seto - Saratoga CA, US
Shobhana Punjabi - San Jose CA, US

G06F 1/32

In one embodiment, a hot swap circuit is disclosed. The hot swap circuit includes a first switch connected to a power input line. The hot swap circuit also includes a first capacitor connected to the first switch that is charged when the first switch is closed. The hot swap circuit further includes a second switch connected to the first switch and the first capacitor. The hot swap circuit additionally includes an input capacitor connected to the second switch and located in parallel with an input line to a power system. When the second switch is closed, the input capacitor is charged.