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Shilpa V Yeole

from San Jose, CA
Age ~48
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Related to:
Omeshwar LawangeVicki Leung
Connected to:
Pritesh S Yeole, 35Yogesh Yeole, 42Ik S Yeom, 62Aubrey Yeoman, 40Carolyn T Yeoman, 80Christina D Yeoman, 54Denise A Yeoman, 43Ericka Yeoman, 54Joanne C Yeoman, 87Keith C Yeoman, 69

Shilpa Yeole Phones & Addresses

  • San Jose, CA
  • 761 Mente Linda Loop, Milpitas, CA 95035 (408) 262-6879 (408) 263-6371
  • 1077 Clifford Ln, Milpitas, CA 95035
  • 440 Dixon Landing Rd, Milpitas, CA 95035 (408) 262-6879

Resumes

Resumes

Shilpa Yeole Photo 1

Staff Engineer

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Location:
Milpitas, CA
Industry:
Semiconductors
Work:
Microsemi Corporation
Staff Engineer
Tabula May 2010 - Apr 2011
Staff Engineer
Tabula Apr 2008 - Apr 2010
Senior Engineer
Actel May 2004 - Jul 2006
Senior Engineer
Education:
San Jose State University 2001 - 2006
Master of Science, Masters, Electrical Engineering
Skills:
Debugging
Eda
Verilog
Simulations
Rtl Design
Soc
Fpga
Embedded Systems
Ic
Tcl
Static Timing Analysis
Asic
Shilpa Yeole Photo 2

Shilpa Yeole

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Publications

Us Patents

Rescaling

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US Patent:
20120176155, Jul 12, 2012
Filed:
Mar 21, 2012
Appl. No.:
13/426592
Inventors:
Scott J. Weber - Piedmont CA, US
Christopher D. Ebeling - San Jose CA, US
Andrew Caldwell - Santa Clara CA, US
Steven Teig - Menlo Park CA, US
Timothy J. Callahan - Mantorville MN, US
Hung Q. Nguyen - San Jose CA, US
Shangzhi Sun - San Jose CA, US
Shilpa V. Yeole - Milpitas CA, US
Assignee:
TABULA, INC. - SANTA CLARA CA
International Classification:
H03K 19/173
G06F 17/50
US Classification:
326 38, 716101
Abstract:
A novel method for designing an integrated circuit (“IC”) by resealing an original set of circuits in a design of the IC is disclosed. The original set of circuits to be resealed includes sequential nodes, combinational nodes, and interconnects. Each sequential node is associated with a phase of a clock. The method generates a resealed set of circuits that includes multiple replica sets of the circuits. Each replica set of circuits includes sequential nodes, combinational nodes, and interconnects that are identical to nodes and interconnects in the original set of circuits. Each sequential node is associated with a phase of a clock that is at a fraction of the phase of its corresponding sequential element in the original set. The method connects nodes in each replica set of circuits to a logically equivalent node in another replica set. The method replaces the original set of circuits with the resealed set of circuits.

Rescaling

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US Patent:
20130097575, Apr 18, 2013
Filed:
Apr 6, 2011
Appl. No.:
13/806767
Inventors:
Scott J. Weber - Piedmont CA, US
Christopher D. Ebeling - San Jose CA, US
Andrew Caldwell - Santa Clara CA, US
Steven Teig - Menlo Park CA, US
Timothy J. Callahan - Mantorville MN, US
Hung Q. Nguyen - San Jose CA, US
Shangzhi Sun - San Jose CA, US
Shilpa V. Yeole - Milpitas CA, US
Assignee:
TABULA, INC. - Santa Clara CA
International Classification:
G06F 17/50
US Classification:
716129, 716134
Abstract:
A novel method for designing an integrated circuit (“IC”) by rescaling an original set of circuits in a design of the IC is disclosed. The original set of circuits to be rescaled includes sequential nodes, combinational nodes, and interconnects. Each sequential node is associated with a phase of a clock. The method generates a rescaled set of circuits that includes multiple replica sets of the circuits. Each replica set of circuits includes sequential nodes, combinational nodes, and interconnects that are identical to nodes and interconnects in the original set of circuits. Each sequential node is associated with a phase of a clock that is at a fraction of the phase of its corresponding sequential element in the original set. The method connects nodes in each replica set of circuits to a logically equivalent node in another replica set. The method replaces the original set of circuits with the rescaled set of circuits.

Rescaling

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US Patent:
20140210512, Jul 31, 2014
Filed:
Jan 28, 2014
Appl. No.:
14/166667
Inventors:
- Santa Clara CA, US
Christopher D. Ebeling - San Jose CA, US
Andrew Caldwell - Santa Clara CA, US
Steven Teig - Menlo Park CA, US
Timothy J. Callahan - Mantorville MN, US
Hung Q. Nguyen - San Jose CA, US
Shangzhi Sun - San Jose CA, US
Shilpa V. Yeole - Milpitas CA, US
Assignee:
Tabula, Inc. - Santa Clara CA
International Classification:
H03K 19/177
US Classification:
326 38
Abstract:
A novel method for designing an integrated circuit (“IC”) by rescaling an original set of circuits in a design of the IC is disclosed. The original set of circuits to be rescaled includes sequential nodes, combinational nodes, and interconnects. Each sequential node is associated with a phase of a clock. The method generates a rescaled set of circuits that includes multiple replica sets of the circuits. Each replica set of circuits includes sequential nodes, combinational nodes, and interconnects that are identical to nodes and interconnects in the original set of circuits. Each sequential node is associated with a phase of a clock that is at a fraction of the phase of its corresponding sequential element in the original set. The method connects nodes in each replica set of circuits to a logically equivalent node in another replica set. The method replaces the original set of circuits with the rescaled set of circuits.
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Shilpa V Yeole from San Jose, CA, age ~48 Get Report