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Sherif R Sweha

from Sacramento, CA
Age ~66
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Also known as:
Sherif R Bsweha, Sherif R B Shewa, Sweha Sweha
Phone and address:
3520 Winding Creek Rd, Sacramento, CA 95864
(916) 974-1464
Related to:
Angelo A Lamola, 84Amir Sweha, 64Sandra Lamola, 84
Connected to:
Danielle Swehla, 38Michael Swehla, 42Ryan S Swehla, 45Lisa J Swei, 56Omar A Sweidan, 49Carolyn A Sweiderk, 57Jill A Sweiderk, 55Abby L Sweigart, 30Alyssa H Sweigart, 27Bill Sweigart, 81

Sherif Sweha Phones & Addresses

  • 3520 Winding Creek Rd, Sacramento, CA 95864 (916) 974-1464
  • 511 Platt Cir, El Dorado Hills, CA 95762
  • Folsom, CA
  • Ann Arbor, MI
  • Berkeley, CA
  • Reno, NV
  • Carmichael, CA
  • PO Box 255265, Sacramento, CA 95865

Resumes

Resumes

Sherif Sweha Photo 1

Principal

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Location:
3520 Winding Creek Rd, Sacramento, CA 95864
Industry:
Semiconductors
Work:
Lattice Semiconductor since Feb 2011
Corporate Vice President of R&D
VIrage Logic (acquired by Synopsys Sept 2010 Jan 2007 - Feb 2011
Vice President of Engineering
International DisplayWorks, Inc Jul 2005 - Dec 2006
Chief Technology Officer
Intel Corporation Jun 1984 - Jun 2005
Senior Director of Design Engineering, Flash Products Group
Texas Instruments Jan 1983 - Jun 1984
Design Engineer, MOS Memory Division
Skills:
Semiconductors
Mixed Signal
Analog
Asic
Cmos
Embedded Systems
Semiconductor Industry
Fpga
Soc
Vlsi
Eda
Debugging
Circuit Design
Ic
Languages:
Arabic
Sherif Sweha Photo 2

Principal

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Location:
Sacramento, CA
Work:
Global Leadership Edge Consultants
Principal
Education:
Louisiana State University 1996 - 2000
Masters Louisiana State University 1981 - 1982
Masters
Sherif Sweha Photo 3

Sherif Sweha

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Location:
Sacramento, CA
Industry:
Semiconductors
Sherif Sweha Photo 4

Sherif Sweha

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Location:
Sacramento, CA
Industry:
Semiconductors
Work:
Lattice Semiconductor
Corp Vp, R and D

Publications

Us Patents

Bit Map Addressing Schemes For Flash Memory

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US Patent:
6483742, Nov 19, 2002
Filed:
Apr 19, 1996
Appl. No.:
08/641046
Inventors:
Sherif Sweha - El Dorado Hills CA
Mark E. Bauer - Cameron Park CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G11C 1604
US Classification:
36518503, 365207, 36523006
Abstract:
Sense path and write path architectures for read and write accesses of a memory device having memory cells that store n binary bits are disclosed. âBy-outputâ architectures provide one output per bit such that each selected memory cell is mapped to n outputs and the n bits stored in the selected memory cell are read in parallel. âBy-addressâ architectures provide one address per bit such that each selected memory cell is mapped to one output, and the n bits stored in the selected memory cell are read sequentially.

Nonvolatile Memory Blocking Architecture

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US Patent:
56639236, Sep 2, 1997
Filed:
Apr 28, 1995
Appl. No.:
8/430882
Inventors:
Robert L. Baltar - Folsom CA
Mark E. Bauer - Cameron Park CA
Kevin W. Frary - Fair Oaks CA
Steven D. Pudar - Sunnyvale CA
Sherif R. Sweha - El Dorado Hills CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G11C 700
US Classification:
36523003
Abstract:
A nonvolatile memory includes a global line and a first block and a second block. The first block includes a plurality of first local lines and a first local decoder coupled to the global line and the first local lines for selectively coupling the global line to one of the first local lines in accordance with an address when the first local decoder is enabled and for isolating the first local lines from the global line when the first local decoder is disabled. The second block includes a plurality of second local lines and a second local decoder coupled to the global line and the second local lines for selectively coupling the global line to one of the second local lines in accordance with the address when the second local decoder is enabled and for isolating the second local lines from the global line when the second local decoder is disabled such that interference between the first and second blocks is eliminated during memory operations.

High-Speed Tri-Level Decoder With Dual-Voltage Isolation

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US Patent:
52742784, Dec 28, 1993
Filed:
Dec 31, 1991
Appl. No.:
7/816155
Inventors:
Mark E. Bauer - Cameron Park CA
Peter Hazen - Sacramento CA
Sherif Sweha - El Dorado Hills CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H03K 1920
H03K 19082
US Classification:
307449
Abstract:
In a memory array in which logic signals of a first and a second voltage levels are used for selecting memory positions in the array for read operations and at least one signal of a voltage level higher than the first and second voltage levels may appear, and including a plurality of wordlines each joined to a common node by individual row decoders, a predecoder circuit for selecting a plurality of wordlines from which a row decoder may select an individual wordline including a full CMOS NAND gate arranged to provide output voltage levels of the first and a second voltage levels, a plurality of weak P channel devices each connected to one of the wordlines, means for operating the weak P channel devices to provide voltage levels of the higher level and below at the wordlines, means for limiting value of voltage transferred to the common point to be less than the higher voltage level, and means for limiting the level of the voltage transferred to the common node from the NAND gate to be less than a predetermined level.

Redundancy Cam Using Word Line From Memory

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US Patent:
50460463, Sep 3, 1991
Filed:
Mar 10, 1978
Appl. No.:
7/321904
Inventors:
Sherif Sweha - Citrus Heights CA
Mark Bauer - Folsom CA
Phil Kliza - Folsom CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G11C 1504
G11C 1134
G11C 700
US Classification:
365200
Abstract:
A redundancy programming circuit employing a two EPROM cell CAM for storing programmed states of redundant elements. The CAMs are disposed aside a memory array and word lines of the array are extended to the CAMs for programming the CAMs. Two word lines are coupled to each EPROM cell so that programming can still be achieved in the event one of the lines is defective.

Apparatus For Increasing The Speed Of Operation Of Non-Volatile Memory Arrays

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US Patent:
52455742, Sep 14, 1993
Filed:
Dec 23, 1991
Appl. No.:
7/812631
Inventors:
Kevin W. Frary - Fair Oaks CA
George Canepa - Folsom CA
Sherif Sweha - El Dorado Hills CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G11C 700
US Classification:
36518909
Abstract:
In a memory array having a plurality of bitlines each connected to a plurality of memory devices having a state in which current is transferred by the memory device and a state in which current is not transferred by the device, a column select device for activating each bitline, a plurality of wordlines for activating individual memory devices joined to each bitline, apparatus for providing constant current in the conducting state of a memory device connected to a bitline, a device connecting a source voltage to a plurality of bitlines, and a reference bitline for providing an output reference signal, the improvement including apparatus for providing a source of current in addition to current through the device connecting a source voltage to a plurality of bitlines in order to charge any capacitance of a selected bitline when that bitline is selected whereby switching between memory devices joined to different bitlines is accelerated.

Bit Map Addressing Schemes For Flash Memory

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US Patent:
57966672, Aug 18, 1998
Filed:
Apr 19, 1996
Appl. No.:
8/639240
Inventors:
Sherif Sweha - El Dorado Hills CA
Mark E. Bauer - Cameron Park CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G11C 700
US Classification:
365207
Abstract:
Sense path and write path architectures for read and write accesses of a memory device having memory cells that store n binary bits are disclosed. "By-output" architectures provide one output per bit such that each selected memory cell is mapped to n outputs and the n bits stored in the selected memory cell are read in parallel. "By-address" architectures provide one address per bit such that each selected memory cell is mapped to one output, and the n bits stored in the selected memory cell are read sequentially.

Bit Map Addressing Schemes For Flash Memory

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US Patent:
54973546, Mar 5, 1996
Filed:
Jun 2, 1994
Appl. No.:
8/253902
Inventors:
Sherif Sweha - El Dorado Hills CA
Mark E. Bauer - Cameron Park CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G11C 800
US Classification:
36523006
Abstract:
Sense path and write path architectures for read and write accesses of a memory device having memory cells that store n binary bits are disclosed. "By-output" architectures provide one output per bit such that each selected memory cell is mapped to n outputs and the n bits stored in the selected memory cell are read in parallel. "By-address" architectures provide one address per bit such that each selected memory cell is mapped to one output, and the n bits stored in the selected memory cell are read sequentially.

Bit Map Addressing Schemes For Flash Memory

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US Patent:
58154434, Sep 29, 1998
Filed:
Apr 19, 1996
Appl. No.:
8/634953
Inventors:
Sherif Sweha - El Dorado Hills CA
Mark E. Bauer - Cameron Park CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G11C 700
US Classification:
36518905
Abstract:
Sense path and write path architectures for read and write accesses of a memory device having memory cells that store n binary bits are disclosed. "By-output" architectures provide one output per bit such that each selected memory cell is mapped to n outputs and the n bits stored in the selected memory cell are read in parallel. "By-address" architectures provide one address per bit such that each selected memory cell is mapped to one output, and the n bits stored in the selected memory cell are read sequentially.
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Sherif R Sweha from Sacramento, CA, age ~66 Get Report