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Sherif H Embabi

from Pearland, TX
Age ~65
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Also known as:
Sherif A Embabi, Sherif K Embabi, Sherif H Embadi, Sherif C Embadi, Sheris Embabi, Mbali E Sherif, Sherif R, Sherif I, Embabi Sheris
Related to:
Dina Embabi SherifAya S Embabi, 33Ahmed S Embabi, 36Dina Matar, 62
Connected to:
Catherine Embach, 75Linda M Embardo, 63Eyob Embaye, 64Sewra H Embaye, 42Anne W Ember, 109Carol R Ember, 81George Ember, 95Jamey W Ember, 62Jennifer R Emberger, 55Jamie Emberley, 29

Sherif Embabi Phones & Addresses

  • Pearland, TX
  • McKinney, TX
  • Dallas, TX
  • 1803 Longwood Ct, Allen, TX 75013 (972) 697-5032
  • Austin, TX
  • Plano, TX
  • Bryan, TX

Resumes

Resumes

Sherif Embabi Photo 1

Director Rf And Analog Ic Engineering At Nvidia

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Position:
Director, RF & Analog IC Engineering at Icera Semiconductor, Director RF and Analog IC Engineering at NVIDIA
Location:
Dallas/Fort Worth Area
Industry:
Semiconductors
Work:
Icera Semiconductor
Director, RF & Analog IC Engineering
NVIDIA - Richardson, TX, USA since Jun 2011
Director RF and Analog IC Engineering
Icera Semiconductor Inc May 2008 - Jun 2011
Director RF and Analog IC Engineering
Texas Instruments 1999 - 2004
Design Manager
Education:
University of Waterloo 1986 - 1991
Ph.D., VLSI
Sherif Embabi Photo 2

Director, Rf & Analog Ic Engineering At Icera Semiconductor

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Position:
Director, RF & Analog IC engineering at Icera Semiconductor
Location:
Dallas/Fort Worth Area
Industry:
Telecommunications
Work:
Icera Semiconductor
Director, RF & Analog IC engineering
Sherif Embabi Photo 3

Senior Director

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Location:
4414 Cedar Springs Rd, Dallas, TX 75219
Industry:
Semiconductors
Work:
Qualcomm
Senior Director
Nvidia Jun 2011 - Jun 2015
Director, Rf and Analog Ic Engineering
Icera Semiconductor Inc May 2008 - Jun 2011
Director, Rf and Analog Ic Engineering
Texas Instruments Aug 1999 - Jul 2004
Design Manager and Rf Ic Design Engineer
Education:
University of Waterloo 1986 - 1991
Doctorates, Doctor of Philosophy Cairo University 1978 - 1983
Bachelors, Bachelor of Science, Electrical Engineering
Skills:
Ic
Integrated Circuit Design
Rf
Analog
Analog Circuit Design
Semiconductors
Cmos
Asic
Mixed Signal
Verilog
Vlsi
Circuit Design
Soc
Cadence Virtuoso
Rtl Design

Publications

Us Patents

Phase Lock Loop

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US Patent:
20020036545, Mar 28, 2002
Filed:
Aug 13, 2001
Appl. No.:
09/929677
Inventors:
Ahmed Fridi - Dallas TX, US
Abdellatif Bellaouar - Dallas TX, US
Sherif Embabi - Plano TX, US
International Classification:
H03L007/00
US Classification:
331/017000
Abstract:
A very fast lock integer N PLL with hybrid digital coarse VCO tuning and VCO temperature drift compensation provides for a fully digital tuning scheme without the need for charge pumps. A PLL synthesizer () using such a PLL design provides for very fast lock times by using an open loop step and a closed loop step. The hybrid PLL can achieve coarse tuning within four clock cycles, while minimizing any errors caused by the VCO non-linearity. Temperature tracking and compensation is also provided. A SAR implementation () and an interpolation tuning implementation () are also described.

Variable Capacitor For Tuned Circuits

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US Patent:
20020040991, Apr 11, 2002
Filed:
May 25, 2001
Appl. No.:
09/866334
Inventors:
Sherif Embabi - Plano TX, US
Abdellatif Bellaouar - Dallas TX, US
International Classification:
H01L029/76
H01L027/108
H01L029/94
H01L031/036
US Classification:
257/312000, 257/067000, 257/068000, 257/130000, 257/206000, 257/390000
Abstract:
A switched variable capacitor (), and binary-weighted array () of such capacitors (), are disclosed. The switched variable capacitor () includes a switching transistor () connected in series with first and second capacitors (), between the two terminals (A,B). Bias transistors () are provided, and of opposite conductivity type as the switching transistor () but with their gates connected to the gate of the switching transistor (). The bias transistors (), when on, apply a reverse bias voltage to the source/drain regions of the switching transistor (), to minimize the parasitic junction capacitance, and thus improve the temperature stability of the capacitor (). A binary-weighted array () of switched variable capacitors () is also disclosed, as is a voltage-controlled oscillator () incorporating such an array ().

System For Reducing Second Order Intermodulation Products From Differential Circuits

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US Patent:
20070132500, Jun 14, 2007
Filed:
Dec 12, 2005
Appl. No.:
11/298667
Inventors:
Sherif Embabi - Plano TX, US
Alan Holden - McKinney TX, US
Jason Jaehnig - Dallas TX, US
Abdellatif Bellaouar - Richardson TX, US
International Classification:
G06F 7/44
US Classification:
327359000
Abstract:
A passive CMOS differential mixer circuit with a mismatch correction circuit for balancing the electrical characteristics of the two output paths. Once the output paths of the differential circuit are balanced, or matched as closely as possible, second order intermodulation product generation can be inhibited or at least reduced to acceptable levels. The mismatch correction circuit receives a digital offset signal, and generates one or more voltage signals to be selectively applied to the signal paths of the passive differential mixer circuit. The voltage signals can be adjusted back gate bias voltages applied to the bulk terminals of selected transistors to adjust their threshold voltages, or the voltage signals can be adjusted common mode voltages applied directly to a selected signal path. Since the differential mixer circuit is passive, no DC current contribution to noise is generated. The switching transistors of the mixer circuit can be maintained at minimal dimensions to reduce switching signal drive loading, resulting in lower power consumption and higher operating frequencies than if larger switching transistors were used.

Edge Power Ramp Using Logarithmic Resistor Attenuator

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US Patent:
20100029228, Feb 4, 2010
Filed:
Dec 20, 2007
Appl. No.:
12/520518
Inventors:
Alan Holden - McKinney TX, US
Hamid Safiri - Plano TX, US
Michel J.G.J.P. Frechette - Plano TX, US
Sherif H.K. Embabi - Plano TX, US
Abdellatif Bellaouar - Richardson TX, US
Stephen Arnold Devison - Waterloo, CA
Tajinder Manku - Waterloo, CA
International Classification:
H04B 1/04
US Classification:
4551271
Abstract:
A power ramping circuit for use in the transmit path of a radio frequency (RF) circuit. The power ramping circuit includes parallel connected transistors used as logarithmic resistor attenuators for adjusting current to a mixer circuit in the transmit path. The parallel connected transistors can be sized differently, and are sequentially turned off to gradually increase the current provided to the mixer circuit. A ramp control circuit controls the parallel connected transistors in response to either an analog signal or a digital signal.

Current Controlled Biasing For Current-Steering Based Rf Variable Gain Amplifiers

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US Patent:
20100093291, Apr 15, 2010
Filed:
Dec 20, 2007
Appl. No.:
12/520513
Inventors:
Sherif H.K. Embabi - Plano TX, US
Abdellatif Bellaouar - Richardson TX, US
Michel J.G.J.P. Frechette - Plano TX, US
International Classification:
H04B 1/04
US Classification:
4551272
Abstract:
An adaptive current control circuit for reduced power consumption and minimized gain shift in a variable gain amplifier. An automatic gain control circuit provides gain control voltages in response to a gain control signal. The gain control voltages are used by the variable gain amplifier to set the gain of the output signal for wireless transmit operations. The adaptive current control circuit receives the same gain control voltages for reducing current to the variable gain amplifier during low gain operation, while providing higher currents during high gain operation. The current that is provided is a hybrid mix of proportional to absolute temperature (PTAT) current and complementary to absolute temperature (CTAT) current for minimizing temperature effects on the gain. The ratio of PTAT current and CTAT current is adjustable for specific temperature ranges to further minimize temperature effects on the gain.

Passive Transmitter Architecture With Switchable Outputs For Wireless Applications

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US Patent:
20110249770, Oct 13, 2011
Filed:
Sep 8, 2009
Appl. No.:
13/062604
Inventors:
Abdellatif Bellaouar - Richardson TX, US
See Taur Lee - Allen TX, US
Sher Jiun Fang - Allen TX, US
Sherif H.K. Embabi - Plano TX, US
Tajinder Manku - Waterloo, Ontario, CA
Assignee:
ICERA INC. - Wilmington DE
International Classification:
H04B 1/04
US Classification:
375296
Abstract:
A transmitter architecture having a single signal path or hardware to cover WCDMA/EDGE/GSM applications, and requires no SAW at the transmitter outputs. The transmitter architecture allows for a transmit convergence feature. A passive mixer with unique driver and furthermore using native devices available from the CMOS process for the mixer cores enables low voltage and low power design, low output noise and high linearity. A digital variable gain amplifier has the capability to cover wide output dynamic range operated from low supply voltage and interfaced digitally with the baseband circuit without DAC. A single transformer is used to combine the outputs from the WCDMA/EDGE and GSM drivers and subsequently convert the differential signal paths into a single-ended signal. RF switches are used to divert the output from the transformer to different bands and applications.

Novel Low Noise Amplifier Architecture For Carrier Aggregation Receivers

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US Patent:
20160173042, Jun 16, 2016
Filed:
Aug 28, 2015
Appl. No.:
14/839055
Inventors:
- Santa Clara CA, US
Frank Zhang - Plano TX, US
Abdellatif Bellaouar - Richardson TX, US
Sherif Embabi - Allen TX, US
International Classification:
H03F 3/193
Abstract:
A low noise amplifier includes a first input transistor coupled to an input signal and a second input transistor coupled to the input signal. The low noise amplifier also includes a first output transistor, coupled between the first input transistor and a first carrier aggregation load, configured to connect the first input transistor to the first carrier aggregation load. Additionally, the low noise amplifier includes a second output transistor, coupled between the first input transistor and a second carrier aggregation load, configured to connect the first input transistor to the second carrier aggregation load. Further, the low noise amplifier includes a third output transistor, coupled between the second input transistor and the second carrier aggregation load, configured to connect the second input transistor to the second carrier aggregation load. Also included are a method of operating a low noise amplifier and an extended carrier low noise amplifier.
Control profile
Sherif H Embabi from Pearland, TX, age ~65 Get Report