Search

Sharon Ann Weintraub

from Western Springs, IL
Age ~56
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Also known as:
Sharon Leitner Weintraub, Sharon Leiter Weintraub, Sharon L Weintraub, Sharon Ann Leiter, Sharon A Leiter, Sharon A Leiter-Weintraub, Sharon B
Phone and address:
3831 Grove Ave, Western Springs, IL 60558
(708) 246-4821
Related to:
James E Vipond, 75
Connected to:
Andrea C Weintraub, 59Benson B Weintraub, 72Cherye K Weintraub, 71Eileen J Weintraub, 113Israel Weintraub, 118Jeanne E Weintraub, 52Jillian T Weintraub, 29Kevin T Weintraub, 28Kristen A Weintraut, 39Leta K Weintraub, 83

Sharon Weintraub Phones & Addresses

  • 3831 Grove Ave, Western Sprgs, IL 60558 (708) 246-4821
  • Western Springs, IL
  • Williamsburg, MI
  • National City, CA
  • San Diego, CA
  • Chicago, IL
  • 3831 Grove Ave, Western Sprgs, IL 60558

Professional Records

Medicine Doctors

Sharon Weintraub Photo 1

Sharon L. Weintraub

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Specialties:
Surgical Critical Care, General Surgery
Work:
Hospital Central Connecticut Surgery
100 Grand St, New Britain, CT 06052
(860) 224-5513 (phone), (860) 224-5713 (fax)
Education:
Medical School
New York University School of Medicine
Graduated: 1995
Procedures:
Endoscopic Retrograde Cholangiopancreatography (ERCP)
Tracheostomy
Appendectomy
Gallbladder Removal
Hemorrhoid Procedures
Hernia Repair
Laparoscopic Appendectomy
Laparoscopic Gallbladder Removal
Nephrectomy
Small Bowel Resection
Spleen Surgey
Thyroid Gland Removal
Conditions:
Intestinal Obstruction
Abdominal Hernia
Appendicitis
Breast Disorders
Cholelethiasis or Cholecystitis
Languages:
English
Description:
Dr. Weintraub graduated from the New York University School of Medicine in 1995. She works in New Britain, CT and specializes in Surgical Critical Care and General Surgery. Dr. Weintraub is affiliated with Hospital Of Central Connecticut.

Publications

Isbn (Books And Publications)

Naughties: Nudies & Bathing Beauties

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Author

Sharon Hope Weintraub

ISBN #

0875884016

Us Patents

System For Asynchronously Transferring Timed Data Using First And Second Clock Signals For Reading And Writing Respectively When Both Clock Signals Maintaining Predetermined Phase Offset

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US Patent:
6581165, Jun 17, 2003
Filed:
Jan 14, 2000
Appl. No.:
09/483520
Inventors:
Sharon Lynn Weintraub - Encinitas CA
Assignee:
Applied Micro Circuits Corporation - San Diego CA
International Classification:
G06F 104
US Classification:
713600, 713400, 713401, 713601, 710 52, 710 58
Abstract:
A system is provided to transfer parallel incoming data from an interface device with an external timing domain, for reading in an internal timing domain, without the use of external control signals. System constraints are reduced by permitting an infinite delay to occur in the byte clock timing through the interface device. The system tolerates a specified drift of the byte clock after initialization which may be the result of thermal changes in the interface device, for example. If the specified drift is exceeded, the system is able to reinitialize timing to reestablish the specified byte clock drift, and so continue the transfer of data from the interface device. A method of transferring data using an internal timing domain, from an interface device having an external timing domain, is also provided.

Precision Digital Delay Element Having Stable Operation Over Varied Manufacturing Processes And Environmental Operating Conditions

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US Patent:
6593791, Jul 15, 2003
Filed:
Apr 3, 2002
Appl. No.:
10/115359
Inventors:
Sharon Lynn Weintraub - Encinitas CA
Assignee:
Applied Micro Circuits Corporation - San Diego CA
International Classification:
H03H 1126
US Classification:
327262, 327269, 327276, 327277, 327298
Abstract:
A digital delay circuit employs a stable reference clock signal, delayed by a reference delay line, to obtain information related to delay characteristics of a matching input delay line. An input clock signal is delayed by the input delay line, which provides a plurality of variously delayed input clock signals based upon the input clock signal. The reference delay line provides a plurality of variously delayed reference clock signals based upon the stable reference clock signal; the delayed reference clock signals convey information related to the operating characteristics of both delay lines. In response to such information, one of the delayed input clock signals can be selected as a delayed clock output. The reference and input delay lines are configured such that the delay circuit consistently generates a delayed clock output having an actual delay that falls within a specified range of delay.

Cascadable Frequency Doubler Having Stable Operation Over Varied Manufacturing Processes And Environmental Operating Conditions

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US Patent:
6597213, Jul 22, 2003
Filed:
Apr 3, 2002
Appl. No.:
10/114835
Inventors:
Sharon Lynn Weintraub - Encinitas CA
Assignee:
Applied Micro Circuits Corporation - San Diego CA
International Classification:
H03B 1900
US Classification:
327122, 327117, 327119, 327262, 327269, 327277, 327298
Abstract:
A digital frequency doubler circuit employs a stable reference clock signal, delayed by a reference delay line, to obtain information related to delay characteristics of a matching input delay line. An input clock signal is delayed by the input delay line, which provides a plurality of variously delayed input clock signals based upon the input clock signal. The reference delay line provides a plurality of variously delayed reference clock signals based upon the stable reference clock signal; the delayed reference clock signals convey information related to the operating characteristics of both delay lines. In response to such information, one of the delayed input clock signals can be selected as a delayed clock output. The reference and input delay lines are configured such that the delay circuit consistently generates a delayed clock output having an actual delay that falls within a specified range of delay. The frequency doubled output clock signal is derived from the delayed clock signal output and the original input clock signal using an XOR element.

Partially-Synchronous High-Speed Counter Circuits

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US Patent:
6445760, Sep 3, 2002
Filed:
Jul 14, 2000
Appl. No.:
09/616125
Inventors:
Sharon Lynn Weintraub - Encinitas CA
Mark Chien-Fu Lin - San Diego CA
Assignee:
Applied Micro Circuits Corporation - San Diego CA
International Classification:
H03K 2100
US Classification:
377 48, 377118
Abstract:
Partially-synchronous and non-integer integrated circuit counters for dividing a high-speed reference clock signal with a selectable divisor have been provided. The circuits use a high-speed synchronous counter that cycles between the use of a selectable and a fixed divisor, to give the counter circuit a selectable overall division ratio. The partially-synchronous counter circuit uses asynchronous dividers to complete the division process and to minimize power consumption. A non-integer counter circuit is provided that includes a edge select mechanism to reduce power consumption in the division process. Examples are presented with specific number of stages, and corresponding divisors and divisor ranges. Method for implementing the above-mentioned partially-synchronous and non-integer counter circuits have also been provided.
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Sharon Ann Weintraub from Western Springs, IL, age ~56 Get Report