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Sharada V Venkateswaran

from San Francisco, CA
Age ~53
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Also known as:
Sharada V Peruvemba, Sarasa Venkateswaran, Sarada Venkataraman, Saradha Venkataraman
Related to:
Coimbatore N VenkataramanC AdimoolamK N VenkateswaranIndirani AdimoolamLakshmi Venkatraman, 49Shanthi Adimoolam, 53Usha VenkateswaranV Shivakumar, 56Rajesh G Peruvemba, 57
Connected to:
Abhishek T Venkatesh, 41Ajay Venkatesan, 44Deepak Venkatesh, 38Gopal Venkatesh, 52Hari K Venkatesan, 43Harsha K Venkatesh, 60Irene Venkatesh, 38Janani Venkatesan, 35Karthikeya Venkatesan, 47Kris Venkatesh, 71

Sharada Venkateswaran Phones & Addresses

  • San Francisco, CA
  • Twain Harte, CA
  • 18661 Harleigh Ct, Saratoga, CA 95070 (408) 370-3597
  • Santa Clara, CA
  • Sunnyvale, CA
  • Milpitas, CA
  • San Jose, CA
  • Cupertino, CA

Work

Company: Oracle corporation Feb 2010 Address: Santa Clara , CA Position: Principal hardware engineer

Education

School / High School: Santa Clara University 1995 to 1997

Skills

Verilog • Rtl Design • Computer Architecture • Soc • Microprocessors • Logic Design • Processors • Debugging • Hardware Design • Vlsi • Ic • Asic • Silicon • Computer Hardware • Architecture • Semiconductor Industry • Semiconductors • Cross Functional Team Leadership

Industries

Semiconductors

Resumes

Resumes

Sharada Venkateswaran Photo 1

Principal Engineer

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Location:
Santa Clara, CA
Industry:
Semiconductors
Work:
Oracle Corporation - Santa Clara , CA since Feb 2010
Principal Hardware Engineer
SUN microsystems - Santa Clara, CA May 2002 - Feb 2010
Staff Engineer
Silicon Access Networks - San Jose, CA Dec 2000 - Dec 2001
Design Engineer
Intel - Santa Clara, CA May 1997 - Dec 2000
Design Engineer
Education:
Santa Clara University 1995 - 1997
Annamalai University
Skills:
Verilog
Rtl Design
Computer Architecture
Soc
Microprocessors
Logic Design
Processors
Debugging
Hardware Design
Vlsi
Ic
Asic
Silicon
Computer Hardware
Architecture
Semiconductor Industry
Semiconductors
Cross Functional Team Leadership

Publications

Us Patents

Shared Data Buffer For Prefetch And Non-Prefetch Entries

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US Patent:
20220188000, Jun 16, 2022
Filed:
Mar 7, 2022
Appl. No.:
17/688611
Inventors:
- Santa Clara CA, US
Sharada Venkateswaran - San Francisco CA, US
Daniel Liu - Santa Clara CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 3/06
Abstract:
An embodiment of an apparatus may comprise one or more substrates and a controller coupled to the one or more substrates, the controller including a read data buffer, a content-addressable memory, and circuitry to track both prefetch read requests and non-prefetch read requests for a memory with the content-addressable memory and to store both prefetch entries and non-prefetch entries in the read data buffer. Other embodiments are disclosed and claimed.

Hybrid Directory And Snoopy-Based Coherency To Reduce Directory Update Overhead In Two-Level Memory

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US Patent:
20200356482, Nov 12, 2020
Filed:
May 7, 2019
Appl. No.:
16/405691
Inventors:
- Santa Clara CA, US
Jeffrey Baxter - Cupertino CA, US
Sai Prashanth Muralidhara - Portland OR, US
Sharada Venkateswaran - San Francisco CA, US
Daniel Liu - Walnut Creek CA, US
Nishant Singh - Bengaluru, IN
Bahaa Fahim - Santa Clara CA, US
Samuel D. Strom - Folsom CA, US
International Classification:
G06F 12/0817
Abstract:
A processor includes one or more cores having cache, a cache home agent (CHA), a near memory controller, to near memory, and a far memory controller, which is to: receive a first memory read operation from the CHA directed at a memory address; detect a miss for the first memory address at the near memory; issue a second memory read operation to the far memory controller to retrieve a cache line, having first data, from the memory address of far memory; receive the cache line from the far memory controller in response to the second memory read operation; and send the cache line to the CHA with a forced change to a directory state of the cache line at the CHA, the forced change to cause the CHA to snoop remote sockets to maintain data coherence for the cache line in an absence of directory state in the far memory.
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Sharada V Venkateswaran from San Francisco, CA, age ~53 Get Report