Shahin N Sharifzadeh

6734108, May 11, 2004

Sep 27, 1999

09/405945

Bo Jin - Campbell CA
Jianmin Qiao - Fremont CA
Shahin Sharifzadeh - Menlo Park CA

Cypress Semiconductor Corporation - San Jose CA

H01L 21302

438700, 438706, 438712

According to one embodiment ( ), a method of forming a self-aligned contact can include forming adjacent conducting structures with sidewalls ( ). A first insulating layer may then be formed without first forming a liner ( ), such as a liner that is conventionally formed to protect underlying conducting structures and/or a substrate. A contact hole may then be etched between adjacent conducting structures ( ). Contact structures may then be formed ( ).

6831346, Dec 14, 2004

May 4, 2001

09/849047

Gabriel Li - San Francisco CA
Kenelm G. D. Murray - Sunnyvale CA
Jose Arreola - Mountain View CA
Shahin Sharifzadeh - Menlo Park CA
K. Nirmal Ratnakumar - San Jose CA

Cypress Semiconductor Corp. - San Jose CA

H01L 2900

257499, 257504, 257509

In an embodiment of an integrated circuit structure having buried layer substrate isolation and a method for forming same, a buried layer having conductivity type opposite to that of an overlying well region is used for wells containing transistors prone to noise generation, where the wells are of the same conductivity type as the substrate. The buried layer may in some embodiments include a first portion underlying the transistor and a second portion spaced apart from and laterally surrounding the first portion. In some embodiments, the circuit may include a doped annular region of the same conductivity type as the buried layer, where the annular region contacts a portion of the buried layer and laterally surrounds the transistor. The circuit may further include metallization adapted to connect the well and annular region to opposite polarities of a power supply voltage, or in some embodiments to preclude such connection.

7773442, Aug 10, 2010

Jun 25, 2004

10/877313

Ravindra M. Kapre - San Jose CA, US
Shahin Sharifzadeh - Menlo Park CA, US

Cypress Semiconductor Corporation - San Jose CA

G11C 7/02

365206, 365228, 365226, 326 21

A complementary field-effect (CMOS) circuit is provided which includes a current-limiting device arranged along a power-supply bus or a ground bus of the circuit. The current-limiting device is configured to prevent latch up of the CMOS circuit. More specifically, the current-limiting device is configured to maintain a junction of the parasitic pnpn diode structure as reverse-biased. A method is also provided which includes creating a current-voltage plot of a pnpn diode arranged within a first CMOS circuit which is absent of a current-limiting device arranged along a power bus of the circuit. In addition, the method includes determining a holding current level from the current-voltage plot and sizing a current-limiting device to place along a power bus of a second CMOS circuit comprising similar design specifications as the first CMOS circuit such that the current through the second CMOS circuit does not exceed the holding current level.

8493804, Jul 23, 2013

Oct 25, 2011

13/280937

Ravindra M. Kapre - San Jose CA, US
Shahin Sharifzadeh - Menlo Park CA, US

Cypress Semiconductor Corporation - San Jose CA

G11C 7/02

365206, 365226, 365228, 326 21

An embodiment includes configuring a current-limiting device to place along a power-supply bus to limit current through a first complimentary-metal-oxide semiconductor (CMOS) circuit coupled to the power-supply bus so that current does not exceed a trigger current level of a pnpn diode in a second CMOS circuit coupled to the power bus.

8045410, Oct 25, 2011

May 1, 2009

12/434084

Ravindra M. Kapre - San Jose CA, US
Shahin Sharifzadeh - Menlo Park CA, US

Cypress Semiconductor Corporation - San Jose CA

G11C 7/02

365206, 365226, 365228, 326 21

A complementary field-effect (CMOS) circuit is provided which includes a current-limiting device arranged along a power-supply bus or a ground bus of the circuit The current-limiting device is configured to prevent latch up of the CMOS circuit. More specifically, the current-limiting device is configured to maintain a junction of the parasitic pnpn diode structure as reverse-biased. A method is also provided which includes creating a current-voltage plot of a pnpn diode arranged within a first CMOS circuit which is absent of a current-limiting device arranged along a power bus of the circuit. In addition, the method includes determining a holding current level from the current-voltage plot and sizing a current-limiting device to place along a power bus of a second CMOS circuit comprising similar design specifications as the first CMOS circuit such that the current through the second CMOS circuit does not exceed the holding current level.

58973710, Apr 27, 1999

Dec 19, 1996

8/769766

Kuantai Yeh - Redwood City CA
Ahmad Chatila - Santa Clara CA
Shahin Sharifzadeh - Menlo Park CA

Cypress Semiconductor Corp. - San Jose CA

H01L 214763

438633

The present invention concerns a process that maintains a second (or "replica") set of alignment marks during existing processing steps used in manufacturing a semiconductor device or integrated circuit, including CMP and other planarization methods. The present invention avoids alignment problems encountered in conventional CMP processes, particularly tungsten CMP. All alignment steps can be realized through one or more subsequent second (or "replica") alignment marks, set and preserved throughout the remaining process steps, thus maintaining alignment integrity. The present method and apparatus concerns a new alignment mark that may be "printed" in a metal layer on the wafer, for example, a local interconnect or contact layer. The new alignment mark is generally not subjected to planarization or to an "open frame" process. The new alignment mark may also be used to re-etch other alignment marks directly onto the layer conventionally causing alignment problems, such as those created following CMP.

20220310843, Sep 29, 2022

Apr 12, 2022

17/719221

- Santa Clara CA, US
Ray Milano - Santa Clara CA, US
Subhash Srinivas Pidaparthi - Santa Clara CA, US
Andrew P. Edwards - Santa Clara CA, US
Hao Cui - Santa Clara CA, US
Shahin Sharifzadeh - Santa Clara CA, US

NEXGEN POWER SYSTEMS, INC. - Santa Clara CA

H01L 29/78
H01L 29/778
H01L 29/66

A method of fabricating a vertical fin-based field effect transistor (FET) includes providing a semiconductor substrate having a first surface and a second surface, the semiconductor substrate having a first conductivity type, epitaxially growing a first semiconductor layer on the first surface of the semiconductor substrate, the first semiconductor layer having the first conductivity type and including a drift layer and a graded doping layer on the drift layer, and epitaxially growing a second semiconductor layer having the first conductivity type on the graded doping layer. The method also includes forming a metal compound layer on the second semiconductor layer, forming a patterned hard mask layer on the metal compound layer, and etching the metal compound layer and the second semiconductor layer using the patterned hard mask layer as a mask exposing a surface of the graded doping layer to form a plurality of fins surrounded by a trench.

20210305404, Sep 30, 2021

Mar 24, 2021

17/211562

- Santa Clara CA, US
Andrew P. Edwards - Santa Clara CA, US
Subhash Srinivas Pidaparthi - Santa Clara CA, US
Shahin Sharifzadeh - Santa Clara CA, US

NEXGEN POWER SYSTEMS, INC. - Santa Clara CA

H01L 29/66
H01L 29/20
H01L 29/08
H01L 29/78

A method of forming an alignment contact includes: providing a III-nitride substrate; epitaxially growing a first III-nitride layer on the III-nitride substrate, wherein the first III-nitride layer is characterized by a first conductivity type; forming a plurality of III-nitride fins on the first III-nitride layer, wherein each the plurality of III-nitride fins is separated by one of a plurality of first recess regions, wherein the plurality of III-nitride fins are characterized by the first conductivity type; epitaxially regrowing a III-nitride source contact portion on each of the plurality of III-nitride fins; and forming a source contact structure on the III-nitride source contact portions.