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Scott K Pozder

from Saratoga Springs, NY
Age ~66
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Also known as:
Scott Foster Pozder, Scott X Pozder, Scott F Pozder
Related to:
Olivia Pozder, 66Piper K Marshall, 71Raymond Marshall, 71Kyle S Marshall, 37Andrew Marshall, 73Andrew Marshall
Connected to:
Marko Pozder, 78Nikita Pozdeyev, 50Sarah K Pozdol, 40Phyllis A Pozdoll, 70Catherine M Pozega, 65John M Pozega, 58Michelle Pozek, 39Patricia Pozella, 67Eugene V Pozen, 43Hector R Pozernick, 46

Scott Pozder Phones & Addresses

  • Saratoga Springs, NY
  • Denver, CO
  • 606 Upson St, Austin, TX 78703 (512) 480-9877
  • 11500 Jollyville Rd, Austin, TX 78759
  • Travis, TX
  • Louisville, CO
  • 606 Upson St, Austin, TX 78703

Work

Company: Globalfoundries Jun 1, 2014 to May 2018 Position: Senior member of technical staff

Education

Degree: Master of Science, Masters School / High School: Colorado School of Mines 2009 to 2011

Skills

Jmp • Wafer Bonding • 3D Wafer and Die Stacking • Plasma Physics • Cadence • Project Management • Software • Xps • Thin Films • Spc • Ic • Cmos • Mems • Silicon • Pecvd • Semiconductors • Design of Experiments • Cvd • Semiconductor Industry • Failure Analysis • Sputtering • Process Integration • Product Engineering • Pvd • Materials Science • Afm • Photolithography • Nanotechnology • Metrology • Device Characterization • Plasma Etch • Etching • Yield • Semiconductor Process • Integrated Circuits

Interests

Kayaking • Environment • Cycling • Hiking • Science and Technology • Animal Welfare

Industries

Nanotechnology

Resumes

Resumes

Scott Pozder Photo 1

Albany, Nowy Jork, Stany Zjednoczone

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Location:
Albany, NY
Industry:
Nanotechnology
Work:
Globalfoundries Jun 1, 2014 - May 2018
Senior Member of Technical Staff
Novati Technologies Inc. Mar 2010 - Jun 2014
Principal Engineer 3D Wafer Bonding and Mems
Quest Product Development Corporation and Quest Manufacturing, Llc Mar 2009 - Mar 2010
Medical Device Consultant
Art-Semi Jun 2009 - Sep 2009
Contract Wafer Bond Engineer
Freescale Semiconductor 2008 - 2009
Package Drm Technologist
Education:
Colorado School of Mines 2009 - 2011
Master of Science, Masters Colorado School of Mines 1992 - 1994
Master of Science, Masters Montana State University - Bozeman 1977 - 1982
Bachelors, Bachelor of Science, Physics
Skills:
Jmp
Wafer Bonding
3D Wafer and Die Stacking
Plasma Physics
Cadence
Project Management
Software
Xps
Thin Films
Spc
Ic
Cmos
Mems
Silicon
Pecvd
Semiconductors
Design of Experiments
Cvd
Semiconductor Industry
Failure Analysis
Sputtering
Process Integration
Product Engineering
Pvd
Materials Science
Afm
Photolithography
Nanotechnology
Metrology
Device Characterization
Plasma Etch
Etching
Yield
Semiconductor Process
Integrated Circuits
Interests:
Kayaking
Environment
Cycling
Hiking
Science and Technology
Animal Welfare

Publications

Us Patents

Method Of Forming An Alternative Ground Contact For A Semiconductor Die

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US Patent:
6420208, Jul 16, 2002
Filed:
Sep 14, 2000
Appl. No.:
09/662079
Inventors:
Scott K. Pozder - Austin TX
Harold A. Downey - Austin TX
Thomas S. Kobayashi - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H01L 2144
US Classification:
438106, 257738
Abstract:
In a semiconductor device, a method forms an alternative ground contact for a semiconductor die in which bulk silicon at the back of a die may be electrically grounded to an area containing functional devices and/or to packaging substrate by conductive fillet material surrounding the die and in contact with the bulk silicon and with a guard ring surrounding the area containing functional devices and/or the packaging substrate.

Method And Apparatus For Manufacturing An Interconnect Structure

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US Patent:
6429531, Aug 6, 2002
Filed:
Apr 18, 2000
Appl. No.:
09/551312
Inventors:
Addi B. Mistry - Austin TX
Rina Chowdhury - Austin TX
Scott K. Pozder - Austin TX
Deborah A. Hagen - Austin TX
Rebecca G. Cole - Austin TX
Kartik Ananthanarayanan - Austin TX
George F. Carney - Mesa AZ
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H01L 2348
US Classification:
257780, 257781, 257784
Abstract:
An interconnect structure, such as a flip-chip structure, including a base pad and a stud formed on the base pad and extending from the base pad is disclosed. The stud and base pad are formed to be continuous and of substantially the same electrically conductive base material. Typically, a solder structure is formed on the stud wherein the solder structure is exposed for subsequent reflow attachment to another structure. The present invention relates to packaging integrated circuits, more particularly to the structure and processing of a stud and bump without the standard under bump metallurgy.

Method Of Forming A Bond Pad And Structure Thereof

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US Patent:
6531384, Mar 11, 2003
Filed:
Sep 14, 2001
Appl. No.:
09/952527
Inventors:
Thomas S. Kobayashi - Austin TX
Scott K. Pozder - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H01L 2144
US Classification:
438612, 438665, 438666, 438738
Abstract:
A bond pad is formed by first providing a planarized combination of copper and silicon oxide features in a bond pad region. The silicon oxide features are etched back to provide a plurality recesses in the copper in the bond pad region. A corrosion barrier is formed over the copper and the silicon oxide features in the recesses. Probing of the wafer is done by directly applying the probe to the copper. A wire bond is directly attached to the copper. The presence of the features improves probe performance because the probe is likely to slip. Also the probe is prevented from penetrating all the way through the copper because the recessed features are present. With the recesses in the copper, the wire bond more readily breaks down and penetrates the corrosion barrier and is also less likely to slip on the bond pad.

Method For Forming A Semiconductor Device Having A Mechanically Robust Pad Interface

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US Patent:
6803302, Oct 12, 2004
Filed:
Nov 22, 1999
Appl. No.:
09/443443
Inventors:
Scott K. Pozder - Austin TX
Thomas S. Kobayashi - Austin TX
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H01L 2144
US Classification:
438612
Abstract:
A composite bond pad that is resistant to external forces that may be applied during probing or packaging operations is presented. The composite bond pad includes a non-self-passivating conductive bond pad ( ) that is formed over a semiconductor substrate ( ). A dielectric layer ( ) is then formed over the conductive bond pad ( ). Portions of the dielectric layer ( ) are removed such that the dielectric layer ( ) becomes perforated and a portion of the conductive bond pad ( ) is exposed. Remaining portions of the dielectric layer ( ) form support structures ( ) that overlie that bond pad. A self-passivating conductive capping layer ( ) is then formed overlying the bond pad structure, where the perforations in the dielectric layer ( ) allow for electrical contact between the capping layer ( ) and the exposed portions of the underlying bond pad ( ). The support structures ( ) provide a mechanical barrier that protects the interface between the capping layer ( ) and the bond pad ( ). Additional mechanical robustness is achieved when the support structures ( ) remain coupled to the unremoved portion of the dielectric layer ( ), as forces buffered by the support structures ( ) are distributed across the dielectric layer ( ) and not concentrated at the bond pad location.

Metal Reduction In Wafer Scribe Area

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US Patent:
6951801, Oct 4, 2005
Filed:
Jan 27, 2003
Appl. No.:
10/351798
Inventors:
Scott K. Pozder - Austin TX, US
Trent S. Uehling - New Braunfels TX, US
Lakshmi N. Ramanathan - Chandler AZ, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H01L021/301
US Classification:
438462, 438460, 438110
Abstract:
A process for removing metal from a scribe area of a semiconductor wafer. The metal removed may include exposed metal in a saw path of the scribe area and the metal in a crack stop trench of the scribe area. In one example, copper is removed from the scribe area by wet etching the wafer. In one example, the wet etching process is performed after the removal of an exposed barrier adhesion layer on the wafer surface. Removal of the metal in the saw path may reduce the amount of metal buildup on a saw blade during singulation of the die areas of a wafer.

Semiconductor Device With Magnetically Permeable Heat Sink

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US Patent:
6958548, Oct 25, 2005
Filed:
Nov 19, 2003
Appl. No.:
10/716655
Inventors:
Scott K. Pozder - Austin TX, US
Michelle F. Rasco - Manor TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H01L023/48
H01L023/10
US Classification:
257783, 257706, 257707, 257782
Abstract:
A semiconductor device is attached to a heat sink by glue that is both thermally conductive and magnetically permeable. The glue fills different features in the surface of the semiconductor device so that there is good coupling between the semiconductor device and the heat sink. The glue is filled with magnetic particles so that the glue is magnetically permeable. The semiconductor device is formed with the heat sink at the wafer level and then singulated after attachment of the heat sink with the glue.

Separately Strained N-Channel And P-Channel Transistors

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US Patent:
7041576, May 9, 2006
Filed:
May 28, 2004
Appl. No.:
10/856581
Inventors:
Scott K. Pozder - Austin TX, US
Salih M. Celik - Austin TX, US
Byoung W. Min - Austin TX, US
Vance H. Adams - Austin TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H01L 21/30
US Classification:
438458, 438109
Abstract:
An integrated circuit with a first plurality of transistors formed on a first wafer and second plurality of transistors formed on a second wafer. At least a substantial majority of the transistor of the first transistor are of a first conductivity type and at least a substantial majority of the transistors of the second plurality are of a second conductivity type. After wafers are bonded together, a portion of the second wafer is removed wherein the strain of the channels of the second plurality of transistors is more compressive than the strain of the channels of the first plurality of transistors.

Semiconductor Device With Magnetically Permeable Heat Sink

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US Patent:
7153726, Dec 26, 2006
Filed:
Aug 26, 2005
Appl. No.:
11/215374
Inventors:
Scott K. Pozder - Austin TX, US
Michelle F. Rasco - Manor TX, US
Assignee:
Freescale Semiconductor, Inc - Austin TX
International Classification:
H01L 21/44
US Classification:
438122, 257E21101
Abstract:
A semiconductor device is attached to a heat sink by glue that is both thermally conductive and magnetically permeable. The glue fills different features in the surface of the semiconductor device so that there is good coupling between the semiconductor device and the heat sink. The glue is filled with magnetic particles so that the glue is magnetically permeable. The semiconductor device is formed with the heat sink at the wafer level and then singulated after attachment of the heat sink with the glue.
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Scott K Pozder from Saratoga Springs, NY, age ~66 Get Report