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Scott J Jewler

from San Luis Obispo, CA
Age ~60
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Also known as:
Scott Joseph Jewler, Scott Joseph Jeweler, Scott J Jeweler
Related to:
Allen J Jewler, 89Maki E Jewler, 57Melissa J Welsh, 62Belle L Jewler, 88Lena M Jewler, 28Keith S Welsh, 73
Connected to:
Yasmin Jewnandan, 53Jasmine J Jews, 35Keith R Jewsbury, 45Michael C Jewsbury, 48Rebecca Jewsbury, 57Melissa B Jewth, 63Adrian A Jex, 43Arlene G Jex, 52Jared R Jex, 51Whitney M Jex, 32

Scott Jewler Phones & Addresses

  • San Luis Obispo, CA
  • 392 Hull Ave, San Jose, CA 95125 (408) 741-1426
  • 14093 Loma Rio Dr, Saratoga, CA 95070 (408) 741-1426
  • Gilbert, AZ
  • Columbia, SC
  • Chandler, AZ
  • Raleigh, NC
  • Santa Clara, CA

Work

Company: Advanced nanotechnology solutions, inc Jun 2012 Position: Senior vice president operations

Education

School / High School: Clemson University 1988 Specialities: Bachelor of Science in Mechanical Engineering

Resumes

Resumes

Scott Jewler Photo 1

Interconnectologist - Semiconductor, Electronics, Operations, Product, Sales, Marketing

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Position:
Interconnectology Consultant at Independant, Co-Founder And Partner at SVXR, LLC
Location:
San Francisco Bay Area
Industry:
Electrical/Electronic Manufacturing
Work:
Independant - Worldwide since Aug 2013
Interconnectology Consultant
SVXR, LLC - Sunnyvale, California since Nov 2012
Co-Founder And Partner
Advanced Nanotechnology Solutions Incorporated - San Jose, CA Jun 2012 - Jul 2013
SVP Operations
Powertech Technology USA - San Jose, CA & Hsinchu, Taiwan Jan 2010 - Jun 2012
Chief Engineering, Sales, and Marketing Officer PTI HQ & President PTI USA
STATS ChipPAC - Singapore Aug 2004 - Aug 2007
Executive Vice President & Chief Strategy Officer, Head of WW Sales and Products
Education:
Clemson University 1983 - 1988
BS, Mechanical Engineering
Honor & Awards:
US Patents USO5623395, USO5790381, USO6281568, USO6455356, and USO6521987
Languages:
English
Japanese
Scott Jewler Photo 2

Scott Jewler Saratoga, CA

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Work:
Advanced Nanotechnology Solutions, Inc

Jun 2012 to Present
Senior Vice President Operations
PTI

Jan 2010 to Present
President
Powertech Technology Inc
San Jose, CA
Jan 2010 to Jun 2012
Powertech Technology Inc

Jan 2011 to Jan 2012
Chief Engineering, Sales, and Marketing Officer
Consultant
2009 to 2009
Ultratech
San Jose, CA
2007 to 2009
Senior Vice President - World Wide Sales, Marketing, and Applications Engineering
STATS ChipPAC, Ltd
Singapore
2004 to 2007
Executive Vice President & Chief Strategy Officer
Amkor Technology Inc

2003 to 2004
President Amkor Technology Taiwan
Amkor Technology Inc
Chandler, AZ
1995 to 2004
Amkor Technology Inc
Chandler, AZ
2001 to 2003
Senior Vice President
Gateway to Management

2001 to 2001
Executive course at Tuck School of Business, Dartmouth University
Amkor Technology Inc
Chandler, AZ
1999 to 2001
Vice President
Amkor Technology Inc
Chandler, AZ
1997 to 1999
Director
Amkor Technology Inc
Chandler, AZ
1995 to 1997
Manager
Mitsubishi Semiconductor, Inc
Durham, NC
1993 to 1995
Section Manager
Mitsubishi Semiconductor, Inc
Durham, NC
1988 to 1995
Mitsubishi Semiconductor, Inc

1992 to 1993
R&D Engineer
Mitsubishi Semiconductor, Inc
Durham, NC
1990 to 1992
Senior Engineer
Mitsubishi Semiconductor, Inc
Durham, NC
1989 to 1990
Project Engineer
Mitsubishi Semiconductor, Inc

1988 to 1989
Engineer Trainee
Education:
Clemson University
1988
Bachelor of Science in Mechanical Engineering
Scott Jewler Photo 3

Scott Jewler

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Business Records

Name / Title
Company / Classification
Phones & Addresses
Scott Jewler
Svxr, LLC
X-Ray Tools and Technology
6060 Guadalupe Mines Ct, San Jose, CA 95120
25 Metro Dr, San Jose, CA 95110

Publications

Us Patents

Methods For Moding A Leadframe In Plastic Integrated Circuit Devices

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US Patent:
6455356, Sep 24, 2002
Filed:
Sep 14, 1999
Appl. No.:
09/395875
Inventors:
Thomas P. Glenn - Gilbert AZ
Scott J. Jewler - Gilbert AZ
David Roman - Tempe AZ
J. H. Yee - Seoul, KR
D. H. Moon - Seoul, KR
Assignee:
Amkor Technology - Chandler AZ
International Classification:
H01L 2148
US Classification:
438123, 438124, 438127, 29827, 29841, 29855
Abstract:
Methods for making packages and leadframes are enclosed. The package includes a die, a die pad, leads, bond wires, and an encapsulant. The lower surfaces of the die pad and leads are provided with a stepped profile by an etching step that etches partially through the thickness of a peripheral portion of the die pad, and also etches partially through the thickness of portions of the leads. Encapsulant material is applied by molding or liquid encapsulation techniques. The encapsulant material fills in beneath the recessed, substantially horizontal surfaces of the die pad and leads formed by the above-described partial etching step, and thereby prevents the die pad and leads from being pulled vertically from the package body. Other surface of the die pad and leads are not covered during the encapsulation step, but rather remain exposed at the lower surface of the package for connecting the package externally. After encapsulation, the die pad and leads are severed from the leadframe, and a completed package is cut from the leadframe.

Plastic Integrated Circuit Device Package And Method For Making The Package

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US Patent:
6521987, Feb 18, 2003
Filed:
Oct 31, 2000
Appl. No.:
09/703195
Inventors:
Thomas P. Glenn - Gilbert AZ
Scott J. Jewler - Gilbert AZ
David Roman - Tempe AZ
Jae Hak Yee - Seoul, KR
Doo Hwan Moon - Seoul, KR
Assignee:
Amkor Technology, Inc. - Chandler AZ
International Classification:
H01L 2312
US Classification:
257684, 257666, 257696, 257698, 257796, 257674, 257675, 257713, 257707, 257730, 257788
Abstract:
A package for an integrated circuit device, having a die, a die pad, leads, bond wire, and an encapsulant. The lower surfaces of the die pad and the leads are provided with stepped profiles. Structures extending from lateral sides of the leads are formed to prevent the leads from being pulled horizontally from the package. Encapsulant material fills beneath the recessed, substantially horizontal surfaces of the die pad and the leads, and thereby prevents the die pad and the leads from being pulled vertically from the package body. Other portions of the die pad and the leads are exposed within the package for connecting the package externally.

Integrated Circuit Package Assembly

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US Patent:
57903816, Aug 4, 1998
Filed:
Feb 28, 1997
Appl. No.:
8/808406
Inventors:
Nour Eddine Derouiche - Raleigh NC
Scott Jewler - Gilbert AZ
Assignee:
Mitsubishi Semiconductor America, Inc. - Durham NC
International Classification:
H05K 702
H05K 712
H01L 2334
US Classification:
361735
Abstract:
SIP or ZIP packages are provided with locking elements of snap fasteners, or have package alignment tabs to combine several IC packages into an IC package assembly. Using a DIP printed circuit board socket, a high density DIP module, for example, a high capacity memory chip, is assembled. The leads of the module are inserted into a motherboard that carries the external conductors to be connected with the inner circuits of the package assembly, and soldered to the motherboard. To make the IC package assembly compatible with a conventional DIP socket, a plastic spacer can be provided between the IC packages. A retaining clip may be used to allow the IC package assembly to be repeatedly inserted and removed to and from the socket without the risk of falling apart.

Plastic Integrated Circuit Device Package And Leadframe Having Partially Undercut Leads And Die Pad

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US Patent:
62815687, Aug 28, 2001
Filed:
Oct 21, 1998
Appl. No.:
9/176614
Inventors:
Thomas P. Glenn - Gilbert AZ
Scott J. Jewler - Gilbert AZ
David Roman - Tempe AZ
J. H. Yee - Seoul, KR
D. H. Moon - Seoul, KR
Assignee:
Amkor Technology, Inc. - Chandler AZ
Anam Semiconductor Inc. - Seoul
International Classification:
H01L 2312
H01L 2328
H01L 2350
US Classification:
257684
Abstract:
Packages for an integrated circuit device and methods and leadframes for making such packages are disclosed. The package includes a die, a die pad, leads, bond wires, and an encapsulant. The lower surfaces of the die pad and leads are provided with a stepped profile by an etching step that etches partially through the thickness of a peripheral portion of the die pad, and also etches partially through the thickness of portions of the leads. Encapsulant material fills in beneath the recessed, substantially horizontal surfaces of the die pad and leads formed by the above-described etching step, and thereby prevents the die pad and leads from being pulled vertically from the package body. Other portions of the die pad and leads are exposed at the lower surface of the package for connecting the package externally. A metal leadframe for making an encapsulated package includes an outer frame.

Integrated Circuit Package Assembly

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US Patent:
56233957, Apr 22, 1997
Filed:
Dec 15, 1995
Appl. No.:
8/572922
Inventors:
Nour E. Derouiche - Raleigh NC
Scott Jewler - Gilbert AZ
Assignee:
Mitsubishi Semiconductor America, Inc. - Durham NC
International Classification:
H05K 702
H05K 712
H01L 2302
H01L 2334
US Classification:
361735
Abstract:
SIP or ZIP packages are provided with locking elements of snap fasteners that allow several packages to be attached to each other to produce an IC package assembly. Using a DIP printed circuit board socket, a high density DIP module, for example, a high capacity memory chip, is assembled. The leads of the module are inserted into a motherboard that carries the external conductors to be connected with the inner circuits of the package assembly, and soldered to the motherboard. To make the IC package assembly compatible with a conventional DIP socket, a plastic spacer can be provided between the IC packages. A retaining clip may be used to allow the IC package assembly to be repeatedly inserted and removed to and from the socket without the risk of falling apart.

Methods And Systems For Printed Circuit Board Design Based On Automatic Corrections

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US Patent:
20210279878, Sep 9, 2021
Filed:
May 20, 2021
Appl. No.:
17/325591
Inventors:
- San Jose CA, US
Freddie Erich Babian - Palo Alto CA, US
Scott Joseph Jewler - San Jose CA, US
International Classification:
G06T 7/00
G06N 20/00
G06T 5/00
G01N 23/04
G01T 1/20
H05K 1/11
H05K 3/40
H01L 21/67
G06F 30/398
G01N 23/083
G01N 23/18
G06K 9/62
Abstract:
In one embodiment, a computing system may access design data of a printed circuit board to be produced by a manufacturing process. The system may determine one or more corrections for the design data of the printed circuit board based on one or more correction rules for correcting one or more parameters associated with the printed circuit board. The system may automatically adjust one or more of the parameters associated with the design data of the printed circuit board based on the one or more corrections. The adjusted parameters may be associated with an impedance of the printed circuit board. The one or more corrections may cause the impendence of the printed circuit board to be independent from layer thickness variations of the printed circuit board to be produced by the manufacturing process.

Methods And Systems For Product Failure Prediction Based On X-Ray Image Re-Examination

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US Patent:
20210010954, Jan 14, 2021
Filed:
Jul 9, 2020
Appl. No.:
16/924706
Inventors:
- San Jose CA, US
Scott Joseph Jewler - San Jose CA, US
Douglas A. Chrissan - Los Gatos CA, US
International Classification:
G01N 23/04
G01N 23/083
G01N 23/18
G06T 7/00
G06K 9/62
Abstract:
In one embodiment, an X-ray inspection system may access a first set of X-ray images of one or more first samples that are labeled as being non-conforming. The system may adjust a classification algorithm based on the first set of X-ray images. The classification algorithm may classify samples into conforming or non-conforming categories based on an analysis of corresponding X-ray images. The system may analyze a second set of X-ray images of a number of second samples using the adjusted classification algorithm. The second samples may be previously inspected samples that have been classified as conforming by the classification algorithm during a previous analysis before the classification algorithm is adjusted. The system may identify one or more of the second samples from the second set of X-ray images. Each identified second sample may be classified as non-conforming by the adjusted classification algorithm.

Methods And Systems For Process Control Based On X-Ray Inspection

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US Patent:
20210011177, Jan 14, 2021
Filed:
Jul 9, 2020
Appl. No.:
16/924663
Inventors:
- San Jose CA, US
Scott Joseph Jewler - San Jose CA, US
International Classification:
G01T 1/20
G01N 23/04
H01L 21/67
Abstract:
In one embodiment, an X-ray inspection system may capture one or more X-ray images for samples of interest processed by a first tool. The X-ray inspection system may be inline with the first tool and have an inspection speed of 300 mmper minute or greater. The system may determine, in real-time, metrology information related to the samples of interest based on the X-ray images. The metrology information may indicate that a sample parameter associated with the samples of interest is outside of a pre-determined range. The system may provide instructions or data to one or more of the first tool or one or more second tools to adjust process parameters associated with the respective tools based on metrology information. The adjusted process parameters may reduce a processing error probability, of the respective tool for processing subsequent samples, related to the sample parameter being outside of the pre-determined range.
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Scott J Jewler from San Luis Obispo, CA, age ~60 Get Report