Sarunya Bangsaruntip

7795677, Sep 14, 2010

Sep 5, 2007

11/850608

Sarunya Bangsaruntip - Mount Kisco NY, US
Guy Moshe Cohen - Mohegan Lake NY, US
Katherine Lynn Saenger - Ossining NY, US

International Business Machines Corporation - Armonk NY

H01L 29/72

257347, 977762, 977784, 977938, 257288

Field-effect transistors (FETs) having nanowire channels are provided. In one aspect, a FET is provided. The FET comprises a substrate having a silicon-on-insulator (SOI) layer which is divided into at least two sections electrically isolated from one another, one section included in a source region and the other section included in a drain region; a channel region connecting the source region and the drain region and including at least one nanowire; an epitaxial semiconductor material, grown from the SOI layer, covering the nanowire and attaching the nanowire to each section of the SOI layer; and a gate over the channel region.

7816275, Oct 19, 2010

Apr 3, 2009

12/417954

Nicholas C. M. Fuller - North Hills NY, US
Sarunya Bangsaruntip - Mount Kisco NY, US
Guy Cohen - Mohegan Lake NY, US
Sebastian U. Engelmann - White Plains NY, US
Lidija Sekaric - Mount Kisco NY, US
Qingyun Yang - Poughkeepsie NY, US
Ying Zhang - Yorktown Heights NY, US

International Business Machines Corporation - Armonk NY

H01L 21/00

438745, 438694, 438197, 257E21001, 977938, 977762

Methodologies and gate etching processes are presented to enable the fabrication of gate conductors of semiconductor devices, such as NFETs and/or PFETs, which are equipped with nano-channels. In one embodiment, a sacrificial spacer of equivalent thickness to the diameter of the gate nano-channel is employed and is deposited after patterning the gate conductor down to the gate dielectric. The residue gate material that is beneath the nano-channel is removed utilizing a medium to high density, bias-free, fluorine-containing or fluorine- and chlorine-containing isotropic etch process without compromising the integrity of the gate. In another embodiment, an encapsulation/passivation layer is utilized. In yet further embodiment, no sacrificial spacer or encapsulation/passivation layer is used and gate etching is performed in an oxygen and nitrogen-free ambient.

7884004, Feb 8, 2011

Feb 4, 2009

12/365623

Sarunya Bangsaruntip - Mount Kisco NY, US
Guy Cohen - Mohegan Lake NY, US
Jeffrey W. Sleight - Ridgefield CT, US

International Business Machines Corporation - Armonk NY

H01L 21/00

438586, 438584, 977762

Semiconductor-based electronic devices and techniques for fabrication thereof are provided. In one aspect, a device is provided comprising a first pad; a second pad and a plurality of nanowires connecting the first pad and the second pad in a ladder-like configuration formed in a silicon-on-insulator (SOI) layer over a buried oxide (BOX) layer, the nanowires having one or more dimensions defined by a re-distribution of silicon from the nanowires to the pads. The device can comprise a field-effect transistor (FET) having a gate surrounding the nanowires wherein portions of the nanowires surrounded by the gate form channels of the FET, the first pad and portions of the nanowires extending out from the gate adjacent to the first pad form a source region of the FET and the second pad and portions of the nanowires extending out from the gate adjacent to the second pad form a drain region of the FET.

8008146, Aug 30, 2011

Dec 4, 2009

12/631148

Sarunya Bangsaruntip - Mount Kisco NY, US
Andres Bryant - Burlington VT, US
Guy Cohen - Mohegan Lake NY, US
Jeffrey W. Sleight - Ridgefield CT, US

International Business Machines Corporation - Armonk NY

H01L 21/8238
H01L 29/76

438211, 438149, 438157, 438200, 438218, 438257, 438258, 438790, 257324, 257329, 257401, 257500, 257501, 257E21625, 257E21629, 257E21679, 257E27081, 257E27103

A method (that produces a structure) patterns at least two wires of semiconductor material such that a first wire of the wires has a larger perimeter than a second wire of the wires. The method performs an oxidation process simultaneously on the wires to form a first gate oxide on the first wire and a second gate oxide on the second wire. The first gate oxide is thicker than the second gate oxide. The method also forms gate conductors over the first gate oxide and the second gate oxide, forms sidewall spacers on the gate conductors, and dopes portions of the first wire and the second wire not covered by the sidewall spacers and the gate conductors to form source and drain regions within the first wire and the second wire.

8097515, Jan 17, 2012

Dec 4, 2009

12/631213

Sarunya Bangsaruntip - Yorktown Heights NY, US
Guy M. Cohen - Yorktown Heights NY, US
Shreesh Narasimha - Yorktown Heights NY, US
Jeffrey W. Sleight - Yorktown Heights NY, US

International Business Machines Corporation - Armonk NY

H01L 21/336
H01L 29/76

438282, 438157, 438198, 438281, 438283, 438458, 257 24, 257347, 257348, 257E21415, 257E21444, 257E29275, 257E29286

A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire over a semiconductor substrate, forming a gate structure around a portion of the nanowire, forming a capping layer on the gate structure; forming a first spacer adjacent to sidewalls of the gate and around portions of nanowire extending from the gate, forming a hardmask layer on the capping layer and the first spacer, removing exposed portions of the nanowire, epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a source region and a drain region, forming a silicide material in the epitaxially grown doped semiconductor material, and forming a conductive material on the source and drain regions.

8119528, Feb 21, 2012

Aug 19, 2008

12/194526

Alejandro G Schrott - New York NY, US
Eric A Joseph - White Plains NY, US
Mary Beth Rothwell - Ridgefield CT, US
Matthew J Breitwisch - Yorktown Heights NY, US
Chung H Lam - Peekskill NY, US
Bipin Rajendran - White Plains NY, US
Sarunya Bangsaruntip - Mount Kisco NY, US

International Business Machines Corporation - Armonk NY

H01L 21/302

438689, 438 95, 438105, 438151, 438692, 438700, 438942, 977762, 977888, 977890, 977895, 216 47, 216 88

A process for preparing a phase change memory semiconductor device comprising a (plurality of) nanoscale electrode(s) for alternately switching a chalcogenide phase change material from its high resistance (amorphous) state to its low resistance (crystalline) state, whereby a reduced amount of current is employed, and wherein the plurality of nanoscale electrodes, when present, have substantially the same dimensions.

8129247, Mar 6, 2012

Dec 4, 2009

12/631205

Sarunya Bangsaruntip - Yorktown Heights NY, US
Josephine B. Chang - Yorktown Heights NY, US
Guy M. Cohen - Yorktown Heights NY, US
Jeffrey W. Sleight - Yorktown Heights NY, US

International Business Machines Corporation - Armonk NY

H01L 21/336

438300, 257E5104, 257E21619, 257E21634, 257E2143, 257103, 438283, 438299

A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire on a semiconductor substrate, forming a first gate structure on a first portion of the nanowire, forming a first protective spacer adjacent to sidewalls of the first gate structure and over portions of the nanowire extending from the first gate structure, removing exposed portions of the nanowire left unprotected by the first spacer, and epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a first source region and a first drain region.

8143113, Mar 27, 2012

Dec 4, 2009

12/630939

Sarunya Bangsaruntip - Yorktown Heights NY, US
Josephine B. Chang - Yorktown Heights NY, US
Isaac Lauer - Yorktown Heights NY, US
Jeffrey W. Sleight - Yorktown Heights NY, US

International Business Machines Corporation - Armonk NY

H01L 21/00

438149, 438151, 977938, 977762, 257E29168

A method for forming a nanowire tunnel field effect transistor device includes forming a nanowire connected to a first pad region and a second pad region, the nanowire including a core portion and a dielectric layer, forming a gate structure on the dielectric layer of the nanowire, forming a first protective spacer on portions of the nanowire, implanting ions in a first portion of the exposed nanowire and the first pad region, implanting in the dielectric layer of a second portion of the exposed nanowire and the second pad region, removing the dielectric layer from the second pad region and the second portion, removing the core portion of the second portion of the exposed nanowire to form a cavity, and epitaxially growing a doped semiconductor material in the cavity to connect the exposed cross sections of the nanowire to the second pad region.