Resumes
Resumes
Sarma Vrudhula
View pageLocation:
United States
Sarma Vrudhula Phones & Addresses
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847 Tamarisk St, Chandler, AZ 85224 (480) 214-3563
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400 Coronado St, Chandler, AZ 85224
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8001 Fort Lowell Rd, Tucson, AZ 85750 (520) 886-6222
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4609 2Nd St, Tucson, AZ 85711
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Santa Monica, CA
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Maricopa, AZ
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Austin, TX
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847 N Tamarisk Ct, Chandler, AZ 85224
Business Records
Name / Title
Company / Classification
Phones & Addresses
USV LLC
847 N Tamarisk Ct, Chandler, AZ 85224
Training Director
Arizona State University
College/University · Consulting Services to Management Students
College/University · Consulting Services to Management Students
350 E Lemon St, Tempe, AZ 85287
PO Box 874106, Tempe, AZ 85287
(480) 965-6201, (480) 965-4154
PO Box 874106, Tempe, AZ 85287
(480) 965-6201, (480) 965-4154
Publications
Wikipedia References
Sarma Bala Vrudhula
Us Patents
Threshold Logic Element Having Low Leakage Power And High Performance
View pageUS Patent:
8164359, Apr 24, 2012
Filed:
Feb 13, 2009
Appl. No.:
12/867352
Inventors:
Samuel Leshner - Mesa AZ, US
Sarma Vrudhula - Chandler AZ, US
Sarma Vrudhula - Chandler AZ, US
Assignee:
Arizona Board of Regents for and on behalf of Arizona State University - Scottsdale AZ
International Classification:
H03K 19/23
US Classification:
326 36, 326 98, 326113
Abstract:
Embodiments of a threshold logic element are provided. Preferably, embodiments of the threshold logic element discussed herein have low leakage power and high performance characteristics. In the preferred embodiment, the threshold logic element is a threshold logic latch (TLL). The TLL is a dynamically operated current-mode threshold logic cell that provides fast and efficient implementation of digital logic functions. The TLL can be operated synchronously or asynchronously and is fully compatible with standard Complementary Metal-Oxide-Semiconductor (CMOS) technology.
Combinational Equivalence Checking For Threshold Logic Circuits
View pageUS Patent:
8181133, May 15, 2012
Filed:
Mar 11, 2009
Appl. No.:
12/401982
Inventors:
Tejaswi Gowda - Tempe AZ, US
Sarma Vrudhula - Chandler AZ, US
Sarma Vrudhula - Chandler AZ, US
Assignee:
Arizona Board of Regents for and on behalf of Arizona State University - Scottsdale AZ
International Classification:
G06F 9/455
G06F 17/50
G06F 17/50
US Classification:
716107
Abstract:
Aspects of a method and system for combinational equivalence checking for threshold logic circuits are provided. In this regard, one or more inputs may be received at a threshold logic gate. The threshold function of the threshold logic gate may be recursively decomposed into a first function and a second function using cofactors of the threshold function. A Boolean function representation of the threshold logic gate may be generated based on the recursive decomposition of the threshold function. The generated Boolean function representation of the threshold logic gate may be a maximally factored form representation of a minimal sum of products (SOP) for the threshold logic gate. A logical equivalence of the threshold logic gate may be verified with one or more other logic circuits based on the generated Boolean function representation of the threshold logic gate.
Decomposition Based Approach For The Synthesis Of Threshold Logic Circuits
View pageUS Patent:
8601417, Dec 3, 2013
Filed:
Apr 20, 2011
Appl. No.:
13/090796
Inventors:
Tejaswi Gowda - Tempe AZ, US
Sarma Vrudhula - Chandler AZ, US
Sarma Vrudhula - Chandler AZ, US
Assignee:
Arizona Board of Regents for and on behalf of Arizona State University - Scottsdale AZ
International Classification:
G06F 17/50
US Classification:
716107, 716101, 716104
Abstract:
Systems and methods for identifying a Boolean function as either a threshold function or a non-threshold function are disclosed. In one embodiment, in order to identify a Boolean function as either a threshold function or a non-threshold function, a determination is first made as to whether the Boolean function satisfies one or more predefined conditions for being a threshold function, where the one or more predefined conditions include a condition that both a positive cofactor and a negative cofactor of the Boolean function are threshold functions. If the one or more predefined conditions are satisfied, a determination is made as to whether weights for the positive and negative cofactors are equal. If the weights for the cofactors are equal, then the Boolean function is determined to be a threshold function. Further, in one embodiment, this threshold function identification process is utilized in a threshold circuit synthesis process.
Threshold Gate And Threshold Logic Array
View pageUS Patent:
20130313623, Nov 28, 2013
Filed:
May 28, 2013
Appl. No.:
13/903490
Inventors:
Sarma Vrudhula - Chandler AZ, US
Nishant S. Nukala - Tempe AZ, US
Niranjan Kulkarni - Phoenix AZ, US
Nishant S. Nukala - Tempe AZ, US
Niranjan Kulkarni - Phoenix AZ, US
Assignee:
Arizona Board of Regents, a body corporate of the State of Arizona, acting for and on behalf of Ariz - Scottsdale AZ
International Classification:
H01L 43/02
US Classification:
257295
Abstract:
Threshold gates and related circuitry are disclosed. In one embodiment, a threshold gate includes a threshold realization element and a magnetic tunnel junction (MTJ) element. The MTJ element is switchable from a first resistive state to a second resistive state. To realize a threshold function with the MTJ element, the threshold realization element is configured to switch the magnetic tunnel junction element from the first resistive state to the second resistive state in accordance with the threshold function. In this manner, the threshold gate may implement a threshold function that provides an output just like a complex Boolean function requiring several Boolean gates.
Technology Mapping For Threshold And Logic Gate Hybrid Circuits
View pageUS Patent:
20130339914, Dec 19, 2013
Filed:
May 28, 2013
Appl. No.:
13/903424
Inventors:
Sarma Vrudhula - Chandler AZ, US
Niranjan Kulkarni - Phoenix AZ, US
Niranjan Kulkarni - Phoenix AZ, US
Assignee:
Arizona Board of Regents, a body corporate of the State of Arizona, acting for and on behalf of Ariz - Scottsdale AZ
International Classification:
G06F 17/50
US Classification:
716104
Abstract:
A method of mapping threshold gate cells into a Boolean network is disclosed. In one embodiment, cuts are enumerated within the Boolean network. Next, a subset of the cuts within the Boolean network that are threshold is identified. To minimize power, cuts in the subset of the cuts are selected.
Method Of Evaluating Integrated Circuit System Performance Using Orthogonal Polynomials
View pageUS Patent:
7630852, Dec 8, 2009
Filed:
Nov 6, 2006
Appl. No.:
11/556766
Inventors:
Praveen Ghanta - Tempe AZ, US
Sarma Vrudhula - Chandler AZ, US
Sarvesh Bhardwaj - Tempe AZ, US
Sarma Vrudhula - Chandler AZ, US
Sarvesh Bhardwaj - Tempe AZ, US
Assignee:
Arizona Board of Regents - Scottdale AZ
International Classification:
G01R 27/28
US Classification:
702117
Abstract:
A method for analyzing IC system performance. The method includes receiving system variables that correspond to an IC system; normalizing the system variables; using an infinite dimensional Hilbert space, modeling a system response as a series of series of orthogonal polynomials; and, solving for coefficients of the series of orthogonal polynomials. A system equation or a simulated response may be used to solve for the coefficients. If a simulated response is used, the coefficients may be solved by using the statistical expectance of the product of the simulated system response and the series of orthogonal polynomials. Alternatively, a simulated system response may be used to generate coefficients by performing a least mean square fit.
Fpga With Reconfigurable Threshold Logic Gates For Improved Performance, Power, And Area
View pageUS Patent:
20210013886, Jan 14, 2021
Filed:
Jul 12, 2020
Appl. No.:
16/926718
Inventors:
Sarma Vrudhula - Chandler AZ, US
Ankit Wagle - Tempe AZ, US
Ankit Wagle - Tempe AZ, US
Assignee:
Arizona Board of Regents on behalf of Arizona State University - Scottsdale AZ
International Classification:
H03K 19/17728
G06F 30/343
G06F 30/347
H03K 19/17796
H03K 19/17736
G06F 30/343
G06F 30/347
H03K 19/17796
H03K 19/17736
Abstract:
A field-programmable gate array (FPGA) with reconfigurable threshold logic gates for improved performance, power, and area (PPA) is provided. This disclosure describes a new architecture for an FPGA, referred to as threshold logic FPGA (TLFPGA), that integrates a conventional lookup table (LUT) with a complementary metal-oxide-semiconductor (CMOS) digital implementation of a binary perceptron, referred to as a threshold logic cell (TLC). The TLFPGA design described herein, combined with a new logic mapping algorithm that exploits the presence of both conventional LUTs and TLCs within the basic logic element (BLE) block, achieves significant improvements in all the metrics of PPA. The TLCs of embodiments described herein are capable of implementing a complex threshold function, which if implemented using conventional gates would require several levels of logic gates. The TLCs only require seven static random-access memory (SRAM) cells and are significantly faster than the conventional LUTs.
Neural Network Circuitry
View pageUS Patent:
20200160159, May 21, 2020
Filed:
Nov 13, 2019
Appl. No.:
16/682233
Inventors:
Elham Azari - Tempe AZ, US
Sarma Vrudhula - Chandler AZ, US
Sarma Vrudhula - Chandler AZ, US
Assignee:
Arizona Board of Regents on behalf of Arizona State University - Scottsdale AZ
International Classification:
G06N 3/063
G06F 13/40
G06N 3/04
G06F 13/40
G06N 3/04
Abstract:
Disclosed is neural network circuitry having a first plurality of logic cells that is interconnected to form neural network computation units that are configured to perform approximate computations. The neural network circuitry further includes a second plurality of logic cells that is interconnected to form a controller hierarchy that is interfaced with the neural network computation units to control pipelining of the approximate computations performed by the neural network computational units. In some embodiments the neural network computation units include approximate multipliers that are configured to perform approximate multiplications that comprise the approximate computations. The approximate multipliers include preprocessing units that reduce latency while maintaining accuracy.