Sarathy P Sribhashyam

6356509, Mar 12, 2002

Dec 5, 2000

09/729869

Saleh M. Abdel-Hafeez - Santa Clara CA
Sarathy P. Sribhashyam - San Jose CA

Sonicblue, Incorporated - Santa Clara CA

G11C 800

365233

A system and method for efficiently implementing a double data rate memory architecture comprises a memory device that includes a memory core with low-footprint memory cells that are configured into even cell rows and odd cell rows. The memory device sequentially performs data transfer operations using the even cell rows and the odd cells rows. The sequential data transfer operations using the even cell rows may be synchronized to a first edge of a periodic clock pulse from a memory clock, and the sequential data transfer operations using the odd cell rows may be synchronized to a second edge of the periodic clock pulse from the memory clock to thereby implement the double data rate memory architecture.

6393600, May 21, 2002

May 26, 1999

09/320191

Sarathy Sribhashyam - Sunnyvale CA
David Hoff - San Jose CA
Nalini Ranjan - San Jose CA

S3 Incorporated - Santa Clara CA

G06F 1750

716 1, 716 7, 365233, 36518905

A word line block, a data block and at least one memory cell form a memory architecture and impose no special timing requirements to handle the synchronization of the outputs of the word line block with the data block. Further, the word line block contains a transmitting transistor and the data block contains a functionally similar transmitting transistor. These transmitting transistors responsive to a write enable signal and a clock signal synchronize a selection signal supplied to the memory cell when data is also supplied to the memory cell. Furthermore, a place in route tool can automatically place and route the word line block, the data block and the at least one memory cell based on chip requirements. Also, with the clock signal proximate the output of the word line block and data block, the place and route tool is able to automatically place and route the blocks and the at least one memory cell to compensate for any calculated interconnection delays. Moreover, since the word line block, the data block, and the at least one memory cell are separate blocks, flexibility is provided in the placement of the blocks as each block requires a reduced amount of layout space as compared to all three blocks together.

7317340, Jan 8, 2008

Feb 28, 2006

11/365068

Sarathy Sribhashyam - San Jose CA, US
David Hoff - Alameda CA, US
Ken Ming Li - Santa Clara CA, US

Altera Coporation - San Jose CA

G01R 29/02
H03K 9/08

327 34, 327 36

An apparatus for compensating for glitch occurrence in a reset signal that is applied in an integrated circuit, includes: a logic stage capable to process an incoming signal and a delayed incoming signal that is a delayed version of the incoming signal, the logic stage capable to generate an output signal so that when the incoming signal and the delayed incoming signal are in the same state, the output signal will be in the same state. An apparatus for compensating for glitch occurrence in a reset signal that is applied in an integrated circuit, includes: a logic stage capable to process an incoming signal and a delayed incoming signal that is a delayed version of the incoming signal, the logic stage capable to generate an output signal so that when the incoming signal and the delayed incoming signal are in the same state, the output signal will have a state similar to the state of the incoming signal, and when the incoming signal and the delayed incoming signal are not in the same state, the output signal will have a state similar to a previously sampled state of the incoming signal.

7405589, Jul 29, 2008

Dec 22, 2005

11/316390

David Lewis - Toronto, CA
Christopher F. Lane - San Jose CA, US
Sarathy Sribhashyam - San Jose CA, US
Srinivas Perisetty - Santa Clara CA, US
Tim Vanderhoek - Toronto, CA
Vaughn Betz - Toronto, CA
Thomas Yau-Tsun Wong - Markham, CA
Andy L. Lee - San Jose CA, US

Altera Corporation - San Jose CA

H03K 19/173

326 38, 327534

A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD.

20080263481, Oct 23, 2008

Jul 1, 2008

12/165665

David Lewis - Toronto, CA
Christopher F. Lane - San Jose CA, US
Sarathy Sribhashyam - San Jose CA, US
Srinivas Perisetty - Santa Clara CA, US
Tim Vanderhoek - Toronto, CA
Vaughn Betz - Toronto, CA
Thomas Yau-Tsun Wong - Markham, CA
Andy L. Lee - San Jose CA, US

G06F 17/50

716 2

A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD.

59031808, May 11, 1999

Jul 24, 1997

8/900084

Yuwen Hsia - Saratoga CA
Sarathy Sribhashyam - Sunnyvale CA

S3 Incorporated - Santa Clara CA

H03L5/00

327333

A voltage tolerant bus hold latch comprises a first buffer transistor, a sense transistor, a low voltage latch, a node voltage controller and a pull-up circuit. The low voltage latch is coupled to the input by the first transistor. The node voltage controller is coupled to the input by the sense transistor. The node voltage controller has a pair of additional inputs coupled to the output of the low voltage latch. The output of the node voltage controller is coupled to control the operation of the pull-up circuit. The pull-up circuit is coupled to the supply voltage for the lower voltage circuitry, and has another control input coupled to the output of the low voltage latch. The output of the pull-up circuit is coupled to the input of the voltage tolerant latch. The pull-up circuit is selectively activated to pull the input of the latch to a high voltage level. The node voltage controller acts as voltage divider to maintain a voltage difference across the gate-to-drain of the pull-up circuit within the operating tolerance of the pull-up circuit (Vtp+2*Vtn).

62081675, Mar 27, 2001

Nov 19, 1997

8/974073

Nalini Ranjan - Sunnyvale CA
Sarathy Sribhashyam - Sunnyvale CA

S3 Incorporated - Santa Clara CA

H03K19/0175

326 81

The present invention provides a buffer for coupling circuitry operating at a low voltage to circuitry operating a high voltage, and vice versa. The buffer outputs signals in a range between the low voltage and a ground voltage lower than the low voltage, and maintains appropriate bias of a semiconductor junction in the buffer using the high voltage. For example, the high voltage can be applied to the body of an output stage pull-up PFET of the buffer to maintain reverse bias between the body and drain of the PFET even when signals at the high voltage are placed on the drain of the PFET by other circuitry. Some embodiments of the present invention include a voltage translator to translate signals output from circuitry operating at the low voltage into a control signal at either the ground voltage or the high voltage. The high voltage of the control signal is beneficial for turning OFF an output stage transistor of the buffer even in the presence of signals at the high voltage on an output of the buffer. The roles of the low and high voltage can also be reversed, for example, by using a ground voltage higher than the high voltage.

59735112, Oct 26, 1999

Jan 5, 1999

9/225650

Yuwen Hsia - San Jose CA
Sarathy Sribhashyam - Sunnyvale CA

S3 Incorporated - Santa Clara CA

H03K 190185

326 81

A voltage tolerant input/output buffer comprises a current mirror, a voltage sensing and isolating circuit, an output pull-up transistor, and an output pull-down transistor. The output pull-up transistor preferably has its gate coupled to the voltage sensing and isolating circuit to receive signals from the lower voltage circuitry, its source coupled to the supply voltage for the lower operating voltage circuitry, and its drain provides the output for connection to the higher voltage circuitry. The voltage sensing and isolating circuit is coupled between the gate and the drain of the output pull-up transistor. The current mirror is coupled to ground and to the voltage sensing and isolating circuit. The output pull-down transistor has its drain coupled to the voltage sensing and isolating circuit, it source coupled to ground, and its gate coupled to receive pull down signals from the lower operating voltage circuit. The current mirror and the voltage sensing and isolating circuit are provided such that as the higher voltage circuit applies a high supply voltage to the drain of the pull-up output transistor, the pull-up output transistor is able to transition to a state at the supply voltage of the lower circuit and sink the current such that the buffer operates properly and correctly, unaffected by the application of the higher operating supply voltage to the drain of the pull-up transistor.