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Sarathy Jayakumar

from Portland, OR
Age ~56
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Also known as:
Thy Jayakumar, Jayakumar Sarathy
Phone and address:
5311 Skycrest Pkwy, Portland, OR 97229
Related to:
Aparna S Jayakumar, 24Anandhi Jayakumar, 49Karthick Sundaram, 48
Connected to:
Aishwariya Jayakumar, 37Francis J Jayakumar, 48Jenani S Jayakumaran, 33John Jayakumar, 81Lalitha M Jayakumar, 73Prabu Jayakumar, 40Radha Jayakumar, 36Rajani Jayakumar, 61Ramesh Jayakumar, 41Sivasamy Jayakumar, 40

Sarathy Jayakumar Phones & Addresses

  • 5311 Skycrest Pkwy, Portland, OR 97229
  • 18090 Cornell Rd, Beaverton, OR 97006
  • 3458 Chelsea Park Ln, Norcross, GA 30092
  • 1737 Sw Harvey Way, Beaverton, OR 97006

Work

Company: Intel corporation Mar 2014 Position: Senior principal engineer

Education

School / High School: Anna University 1990 to 1992 Specialities: Electronics

Skills

Firmware • Bios • Debugging • Device Drivers • X86 • Embedded Systems • Computer Architecture • Processors • Embedded Software • Pcie • Intel • System Architecture • C • Usb • Microprocessors • Soc • Hardware Architecture • C++ • X86 Assembly • Linux Kernel • Embedded Linux • Verilog • Asic • Arm • Ic • Embedded C • Sata • Kernel • File Systems • Rtos • Scsi • Fpga • Systemverilog • Real Time Operating Systems • Technical Marketing • Field Programmable Gate Arrays • I2C • System on A Chip • Application Specific Integrated Circuits

Languages

German • Tamil • English • Telugu • Hindi

Industries

Semiconductors

Resumes

Resumes

Sarathy Jayakumar Photo 1

Senior Principal Engineer

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Location:
Portland, OR
Industry:
Semiconductors
Work:
Intel Corporation
Senior Principal Engineer
Intel Corporation Mar 2007 - Feb 2014
Senior Staff Engineer
Intel Corporation Mar 2002 - Feb 2007
Staff Engineer
Intel Corporation Dec 1999 - Mar 2002
Senior Software Engineer
American Megatrends India Pvt Ltd Jun 1995 - Dec 1999
Senior Software Engineer
Education:
Anna University 1990 - 1992
Coimbatore Institute of Technology 1985 - 1989
Bachelor of Engineering, Bachelors Bharathiar University College of Arts and Science 1985 - 1989
Bachelor of Engineering, Bachelors, Communication, Electronics
Skills:
Firmware
Bios
Debugging
Device Drivers
X86
Embedded Systems
Computer Architecture
Processors
Embedded Software
Pcie
Intel
System Architecture
C
Usb
Microprocessors
Soc
Hardware Architecture
C++
X86 Assembly
Linux Kernel
Embedded Linux
Verilog
Asic
Arm
Ic
Embedded C
Sata
Kernel
File Systems
Rtos
Scsi
Fpga
Systemverilog
Real Time Operating Systems
Technical Marketing
Field Programmable Gate Arrays
I2C
System on A Chip
Application Specific Integrated Circuits
Languages:
German
Tamil
English
Telugu
Hindi

Publications

Us Patents

Bi-Directional Handshake For Advanced Reliabilty Availability And Serviceability

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US Patent:
8402186, Mar 19, 2013
Filed:
Jun 30, 2009
Appl. No.:
12/459423
Inventors:
Sarathy Jayakumar - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 13/42
G06F 12/00
G06F 13/14
G06F 13/38
US Classification:
710105, 710240, 710242
Abstract:
In some embodiments a signal is sent from a Basic Input/Output System to a device to indicate that the Basic Input/Output System needs to obtain control of shared resources. A signal is sent from the device to the Basic Input/Output System that indicates that the Basic Input/Output System can now control the shared resources. Other embodiments are described and claimed.

Controlling Memory Redundancy In A System

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US Patent:
8407516, Mar 26, 2013
Filed:
Dec 23, 2009
Appl. No.:
12/645778
Inventors:
Robert C. Swanson - Olympia WA, US
Mahesh S. Natu - Sunnyvale CA, US
Rahul Khanna - Portland OR, US
Murugasamy K. Nachimuthu - Beaverton OR, US
Sarathy Jayakumar - Portland OR, US
Anil S. Keshavamurthy - Portland OR, US
Narayan Ranganathan - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 11/00
US Classification:
714 623
Abstract:
In one embodiment, the present invention provides an ability to handle an error occurring during a memory migration operation in a high availability system. In addition, a method can be used to dynamically remap a memory page stored in a non-mirrored memory region of memory to a mirrored memory region. This dynamic remapping may be responsive to a determination that the memory page has been accessed more than a threshold number of times, indicating a criticality of information on the page. Other embodiments are described and claimed.

Firmware Assisted Error Handling Scheme

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US Patent:
8448024, May 21, 2013
Filed:
May 16, 2007
Appl. No.:
11/804105
Inventors:
Mohan Kumar - Aloha OR, US
Sarathy Jayakumar - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 11/00
US Classification:
714 25, 714 44, 714 48
Abstract:
A firmware assisted error handling scheme in a computer system has been disclosed. In one embodiment, firmware is used to access one or more hardware-specific error registers within the computer system in response to a system management interrupt (SMI) trap. Using the firmware, an error record in a common error record format is constructed. The error record is made available to an operating system (OS) within the computer system.

Logic Device Having Status And Control Registers For Recording The Status And Controlling The Operation Of Memory Slots Such That Each Memory Slot Is Identified Using A Bus Address And Port Number

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US Patent:
8650414, Feb 11, 2014
Filed:
Sep 24, 2010
Appl. No.:
12/890222
Inventors:
Sarathy Jayakumar - Portland OR, US
Gopal R. Mundada - Olympia WA, US
Palsamy Sakthikumar - Puyallup WA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1/00
G06F 13/00
G06F 3/00
G06F 11/00
US Classification:
713300, 710302, 710104, 710 8, 714 12
Abstract:
Memory reconfiguration during system run-time is described. In one example, a system includes a memory slot to carry a memory board and to connect the memory board to a memory controller for read and write operations, a logic device having a plurality of status registers to record the status of the memory slot and a plurality of control registers to control the operation of the memory slot, and a bus interface coupled through direct signal lines to the memory slot to communicate status and control signals with the memory slot and coupled through a serial bus to the logic device to communicate status and control signals with the logic device.

Methods And Apparatus For Generating System Management Interrupts

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US Patent:
20090172372, Jul 2, 2009
Filed:
Dec 31, 2007
Appl. No.:
11/967299
Inventors:
Mohan J. Kumar - Aloha OR, US
Sarathy Jayakumar - Portland OR, US
Sham Datta - Hillsboro OR, US
International Classification:
G06F 9/26
US Classification:
712244, 712E09015
Abstract:
A method includes determining a plurality of memory addresses, each memory address being different from one another. The method further includes generating a plurality of system management interrupt interprocessor interrupts, each system management interrupt interprocessor interrupt having a corresponding processor in a plurality of processors in a system and each system management interrupt interprocessor interrupt including one of the plurality of memory addresses. The method further includes directing each system management interrupt interprocessor interrupt to the corresponding processor. An associated machine readable medium is also disclosed.

Injecting Error And/Or Migrating Memory In A Computing System

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US Patent:
20110179311, Jul 21, 2011
Filed:
Dec 17, 2010
Appl. No.:
12/971868
Inventors:
Murugasamy K. Nachimuthu - Beaverton OR, US
Mohan J. Kumar - Aloha OR, US
Sarathy Jayakumar - Portland OR, US
Chung-Chi Wang - Sunnyvale CA, US
International Classification:
G06F 11/00
US Classification:
714 42, 714E11144
Abstract:
In some embodiments a request is received to perform an error injection or a memory migration, a mode is entered that blocks requests from agents other than a current processor core or thread, the error is injected or the memory is migrated, and the mode that blocks requests from the agents other than the current processor core or thread is exited. Other embodiments are described and claimed.

Computing Platform Interface With Memory Management

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US Patent:
20130151569, Jun 13, 2013
Filed:
Nov 21, 2012
Appl. No.:
13/683748
Inventors:
Guy Therien - Beaverton OR, US
Paul Diefenbaugh - Portland OR, US
Anil Aggarwal - Portland OR, US
Andrew Henroid - Portland OR, US
Jeremy Shrall - Portland OR, US
Efraim Rotem - Haifa, IL
Krishnakanth Sistla - Beaverton OR, US
Eliezer Weissmann - Haifa, IL
Mohan Kumar - Aloha OR, US
Sarathy Jayakumar - Portland OR, US
Jose Andy Vargas - Rescue CA, US
Neelam Chandwani - Portland OR, US
Michael A. Rothman - Puyallup WA, US
Robert Gough - Sherwood OR, US
Mark Doran - Olympia WA, US
International Classification:
G06F 17/30
US Classification:
707803
Abstract:
In some embodiments, a PPM interface may be provided with functionality to facilitate to an OS memory power state management for one or more memory nodes, regardless of a particular platform hardware configuration, as long as the platform hardware is in conformance with the PPM interface.

Controlling Memory Redundancy In A System

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US Patent:
20130212426, Aug 15, 2013
Filed:
Mar 22, 2013
Appl. No.:
13/848830
Inventors:
Robert C. Swanson - Olympia WA, US
Mahesh S. Natu - Sunnyvale CA, US
Rahul Khanna - Portland OR, US
Murugasamy K. Nachimuthu - Beaverton OR, US
Sarathy Jayakumar - Portland OR, US
Anil S. Keshavamurthy - Portland OR, US
Narayan Ranganathan - Portland OR, US
International Classification:
G06F 11/20
US Classification:
714 63
Abstract:
In one embodiment, the present invention provides an ability to handle an error occurring during a memory migration operation in a high availability system. In addition, a method can be used to dynamically remap a memory page stored in a non-mirrored memory region of memory to a mirrored memory region. This dynamic remapping may be responsive to a determination that the memory page has been accessed more than a threshold number of times, indicating a criticality of information on the page. Other embodiments are described and claimed.
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Sarathy Jayakumar from Portland, OR, age ~56 Get Report