Inventors:
Shan-Chyun Ku - Hsinchu, TW
Marcelo Glusman - San Jose CA, US
Yee-Wing Hsieh - Pleasanton CA, US
Manish Pandey - Saratoga CA, US
Angela Krstic - San Diego CA, US
Sarath Kirihennedige - Fremont CA, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 17/50
G06F 9/455
US Classification:
716108, 716111, 716113, 716114, 716122, 716134, 716136
Abstract:
Certain embodiments of the present invention enable comparisons between constrained circuit designs by generating timing graphs for circuit designs, mapping timing constraints to the timing graphs, and comparing the mapped timing constraints from different timing graphs. Typically this comparison is made by identifying corresponding nodes in two or more timing graphs. Specific embodiments are also directed to multiple SDC (Synopsis Design Constraint) constraint specifications for a circuit and multiple constraint sets for different operational modes of a circuit.