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Santiago Fernandez-Gomez

from Sunnyvale, CA
Age ~53

Santiago Fernandez-Gomez Phones & Addresses

  • Sunnyvale, CA
  • 1690 Civic Center Dr, Santa Clara, CA 95050
  • Mountain View, CA
  • Menlo Park, CA

Business Records

Name / Title
Company / Classification
Phones & Addresses
Santiago Fernandez-Gomez
Mind Spaces, LLC
Engineering Management Consulting · Engineering Services
2360 Corporate Cir, Henderson, NV 89074
1160 Snowberry Ct, Sunnyvale, CA 94087

Publications

Us Patents

System For Handling Memory Requests And Method Thereof

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US Patent:
7240157, Jul 3, 2007
Filed:
Sep 26, 2001
Appl. No.:
09/963861
Inventors:
Michael Frank - Sunnyvale CA,
Santiago Fernandez-Gomez - Menlo Park CA,
Robert W. Laker - Fremont CA,
Aki Niimura - Sunnyvale CA,
Assignee:
ATI Technologies, Inc. - Toronto, Ontario
International Classification:
G06F 12/00
US Classification:
711118, 711133, 711136, 711141, 711160
Abstract:
A system and methods are shown for handling multiple target memory requests. Memory read requests generated by a peripheral component interconnect (PCI) client are received by a PCI bus controller. The PCI bus controller passes the memory request to a memory controller used to access main memory. The memory controller passes the memory request to a bus interface unit used to access cache memory and a processor. The bus interface unit determines if cache memory can be used to provide the data associated with the PCI client's memory request. While the bus interface unit determines if cache memory may be used, the memory controller continues to process the memory request to main memory. If cache memory can be used, the bus interface unit provides the data to the PCI client and sends a notification to the memory controller. The memory controller identifies the memory request, or returned data associated with the request, and discards it to ensure no data is returned to the bus controller from the memory controller. Once the data is received from the bus interface unit, the bus controller is free to send new memory read requests to the memory controller.

Integrated Circuit Having Secure Access To Test Modes

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US Patent:
8120377, Feb 21, 2012
Filed:
Jun 26, 2009
Appl. No.:
12/492427
Inventors:
Jianlin Yu - Cupertino CA,
Michael Frank - Sunnyvale CA,
Erik P. Machnicki - San Jose CA,
Jerrold V. Hauck - Windermere FL,
Jean-Didier Allegrucci - Sunnyvale CA,
Santiago Fernandez-Gomez - Sunnyvale CA,
Assignee:
Apple Inc. - Cupertino CA
International Classification:
G01R 31/26
US Classification:
32476201, 3247503
Abstract:
Methods for enabling a secure test mode, and integrated circuits (IC's) implementing the same are disclosed. An IC may include a secure functional unit that is protected from access from test access circuitry during normal operation. The secure functional unit may be rendered inaccessible the test access circuitry of the IC following a completion of a test that includes testing of the secure functional unit. An embodiment of an IC that includes circuitry to delay entry into a test mode while a chip-level reset is performed is also contemplated. Entry into the test mode may be delayed until all circuitry of the IC has been fully reset in order to clear stored information.

Secure Register Scan Bypass

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US Patent:
8495443, Jul 23, 2013
Filed:
May 31, 2011
Appl. No.:
13/149134
Inventors:
Jianlin Yu - Cupertino CA,
Santiago Fernandez-Gomez - Sunnyvale CA,
Samy Makar - Fremont CA,
Assignee:
Apple Inc. - Cupertino CA
International Classification:
G01R 31/28
US Classification:
714729, 714730
Abstract:
An apparatus and method for protecting the contents of a secure register from scan accessibility is disclosed. The secure register may include a number of scannable elements within a scan chain. During a normal scan test mode, the scannable elements of the secure register may be accessibly, as data may be shifted to, from, or through these elements. During certain other modes (e. g. , a scan dump or memory dump), a bypass circuit may be invoked to effectively separate the scan elements associated with the secure register from the remainder of the scan chain. During operation in one of these modes, no data may be shifted to, from, or through the scan elements of the secure register. Accordingly, the bypass path may protect secure data stored in the secure register from unauthorized access.

Memory Content Protection During Scan Dumps And Memory Dumps

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US Patent:
8589749, Nov 19, 2013
Filed:
May 31, 2011
Appl. No.:
13/149194
Inventors:
Jianlin Yu - Cupertino CA,
Santiago Fernandez-Gomez - Sunnyvale CA,
Assignee:
Apple Inc. - Cupertino CA
International Classification:
G01R 31/3177
G01R 31/327
US Classification:
714729, 714733
Abstract:
A method and apparatus for preventing the overwriting of memory contents during certain scan operations is disclosed. An integrated circuit (IC) may include a memory and a scan chain having a number of serially coupled scan elements. A number of the scan elements may be coupled to circuitry for inputting signals to or receiving signals output from the memory. An inhibit circuit may also be coupled to the circuitry for inputting signals to the memory. During scan shifting operations commensurate with a scan dump mode or a memory dump mode, the inhibit circuit may de-assert one or more control signals that otherwise enable access to the memory in order to prevent shifted data from overwriting the contents stored in the memory. The apparatus may also include a bypass unit coupled to a memory read port, which can be activated to prevent unauthorized access to protected data stored in the memory.

Memory Controller System And Methods Thereof

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US Patent:
20030159013, Aug 21, 2003
Filed:
Feb 19, 2002
Appl. No.:
10/078821
Inventors:
Michael Frank - Sunnyvale CA,
Santiago Fernandez-Gomez - Menlo Park CA,
Robert Laker - Fremont CA,
Aki Niimura - Sunnyvale CA,
International Classification:
G06F012/00
US Classification:
711/169000, 711/154000
Abstract:
A method and system are shown for bypassing memory controller components when processing memory requests. A memory controller analyzes internal components to determine if any pending memory requests exist. If particular memory controller components are idle, a memory client is informed that a bypassing of memory controller components is possible. A bypass module of the memory controller receives memory requests from the memory client. The bypass module examines memory controller parameters and a configuration of main memory to determine which memory controller components may be bypassed and routes the memory request accordingly. In a system with asynchronous memory, the memory controller provides copies of the memory request through a dual pipeline. A first copy of the memory request is processed through a bypass module to attempt to bypass memory controller components. A second copy of the memory request is processed in a normal fashion in case a bypass of the memory access request is not possible. If the bypass is possible, the second memory request is cancelled.

System For Handling Memory Requests And Method Thereof

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US Patent:
20070255904, Nov 1, 2007
Filed:
Apr 24, 2007
Appl. No.:
11/739322
Inventors:
Michael Frank - Sunnyvale CA,
Santiago Fernandez-Gomez - Menlo Park CA,
Robert Laker - Fremont CA,
Aki Niimura - Sunnyvale CA,
Assignee:
ATI TECHNOLOGIES, INC. - Markham
International Classification:
G06F 12/08
US Classification:
711118000
Abstract:
A system and methods are shown for handling multiple target memory requests. Memory read requests generated by a peripheral component interconnect (PCI) client are received by a PCI bus controller. The PCI bus controller passes the memory request to a memory controller used to access main memory. The memory controller passes the memory request to a bus interface unit used to access cache memory and a processor. The bus interface unit determines if cache memory can be used to provide the data associated with the PCI client's memory request. While the bus interface unit determines if cache memory may be used, the memory controller continues to process the memory request to main memory. If cache memory can be used, the bus interface unit provides the data to the PCI client and sends a notification to the memory controller. The memory controller identifies the memory request, or returned data associated with the request, and discards it to ensure no data is returned to the bus controller from the memory controller. Once the data is received from the bus interface unit, the bus controller is free to send new memory read requests to the memory controller.
Santiago Fernandez-Gomez from Sunnyvale, CA, age ~53 Get Report