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Sanjay Dabral

from Cupertino, CA
Age ~59
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Also known as:
Shane Dabral
Phone and address:
10439 Ann Arbor Ave, Cupertino, CA 95014
Related to:
Daniel Flores, 48Cristal Banuelos, 34Laura Alicia Banuelos, 54Tushar Dabral, 45
Connected to:
Vinod K Dabral, 72Linda M Dabrea, 72Brian A Dabreo, 31Terrence F Dabreo, 58Victor O Dabreo, 71Gordon A Dabreu, 33Helen B Dabreu, 79Joanna I Dabrowiecka, 46Adreen S Dabrowski, 40Arthur Dabrowski, 47

Sanjay Dabral Phones & Addresses

  • 10439 Ann Arbor Ave, Cupertino, CA 95014
  • Santa Clara, CA
  • 4125 Sutherland Dr, Palo Alto, CA 94303
  • Milpitas, CA
  • Troy, NY

Publications

Us Patents

Charge Sharing And Charge Recycling For An On-Chip Bus

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US Patent:
6356115, Mar 12, 2002
Filed:
Aug 4, 1999
Appl. No.:
09/368639
Inventors:
Sanjay Dabral - Milpitas CA
Ming Zeng - San Jose CA
Subramaniam Maiyuran - Fair Oaks CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H03K 19094
US Classification:
326 86, 326 30, 326 90, 326 98, 327 28, 327 77, 327379, 365203, 365205, 365207
Abstract:
A method for charge sharing among data conductors of a bus. The bus has a first data conductor and a corresponding data conductor. The method includes detecting the logic levels on the first data conductor and the corresponding data conductor, and generating a charge sharing signal for sharing charge between the first data conductor and the corresponding data conductor.

Apparatus And Methods For Multi-Lingual User Access

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US Patent:
6370498, Apr 9, 2002
Filed:
Jun 15, 1998
Appl. No.:
09/094886
Inventors:
Maria Ruth Angelica Flores - Stanford CA, 94305
Sanjay Dabral - Milpitas CA, 95035
International Classification:
G06F 1728
US Classification:
704 3, 707536
Abstract:
An apparatus and method for the multi-lingual creation and retrieval of a work from a database storing multiple texts and/or translations of works in a variety of formats. A user can create and retrieve multiple translations of a work and may choose to have the multiple texts and/or translations presented in different formats. For example, the user may choose to have a document displayed textually in two separate languages, or in text in one language and in audio in a second language.

Orienting Multiple Processors On Two Sides Of A Printed Circuit Board

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US Patent:
6373715, Apr 16, 2002
Filed:
Dec 17, 1999
Appl. No.:
09/467300
Inventors:
Ming Zeng - San Jose CA
Sanjay Dabral - Milpitas CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H05K 702
US Classification:
361760
Abstract:
A topology for mounting processors on opposite sides of a printed circuit board (PCB) orients rows of processor connection pins parallel to the bus orientation within the PCB and defines a relative 180 degree orientation between the opposing processors.

Low Cost And High Speed 3-Load Printed Wiring Board Bus Topology

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US Patent:
6417462, Jul 9, 2002
Filed:
Jun 19, 2000
Appl. No.:
09/596613
Inventors:
Sanjay Dabral - Milpitas CA
Ming Zeng - San Jose CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01R 909
US Classification:
174261, 174260, 174262, 257778
Abstract:
A multi layer printed circuit board with a 3-load topology is disclosed. First, second, and third integrated circuit (IC) printed wiring board packages having first, second, and third sets of terminals respectively are mounted on opposite sides of the board so that the second set of terminals are directly opposite the third set of terminals. Each package contains an IC die coupled to the respective set of terminals. The IC die in the first package is substantially identical to the one contained in the second package, and different than the one contained in the third package. For improved fanout of the metal lines that interconnect the first package to the second and third packages, each of the first, second, and third sets of terminals in the packages is arranged in substantially a U-shape. Each set of terminals has the same set of signal assignments of a parallel bus implemented by metal lines in the board. The 3-load topology is particularly useful for personal computer motherboard units having twin processors and a bridge chip set, yielding a motherboard having significantly lower number of metal layers, a faster bus and significantly improved noise margin, all with high density IC packages on a wide parallel bus.

Method And Apparatus For Implementing A Highly Robust, Fast, And Economical Five Load Bus Topology Based On Bit Mirroring And A Well Terminated Transmission Environment

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US Patent:
6417688, Jul 9, 2002
Filed:
Dec 31, 1999
Appl. No.:
09/476585
Inventors:
Sanjay Dabral - Palo Alto CA
Ming Zeng - San Jose CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H03K 1716
US Classification:
326 30, 326 82, 326 86, 326 90, 361760
Abstract:
In one embodiment, the invention is a method of forming a bus. A first conductor having a first impedance is provided, the first conductor is routed through a fifth chip. Coupling of the first conductor to a first chip with a first termination impedance occurs. Coupling of the first conductor to a second chip with a second termination impedance occurs. Coupling of the first conductor to a third chip with a third termination impedance occurs, and coupling of the first conductor to a fourth chip with a fourth termination impedance occurs.

Apparatus For Interconnecting Multiple Devices On A Circuit Board

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US Patent:
6434016, Aug 13, 2002
Filed:
May 4, 2001
Appl. No.:
09/848996
Inventors:
Ming Zeng - San Jose CA
Sanjay Dabral - Palo Alto CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H05K 118
US Classification:
361760, 361764, 361765, 361777, 257698, 257773, 257774, 174255, 174260262-, 174266, 22818021, 22818022
Abstract:
A method and apparatus interconnecting multiple devices on a circuit board. One disclosed circuit board has a first attach region on a first surface for coupling a first set of pins from a first device to a set of signal lines. A second attach region on a second surface is for coupling a second set of pins from a second device to the set of signal lines. The second attach region is predominantly non-overlapping with respect to the first attach region.

Reference Voltage Distribution For Multiload I/O Systems

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US Patent:
6453422, Sep 17, 2002
Filed:
Dec 23, 1999
Appl. No.:
09/470686
Inventors:
Sanjay Dabral - Milpitas CA
Stephen R. Mooney - Beaverton OR
T. Zale Schoenborn - Portland OR
Sam E. Calvin - Phoenix AZ
Tim Frodsham - Portland OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 126
US Classification:
713300, 710100, 307147, 375257, 379 90, 327537, 327538, 327546
Abstract:
According to an embodiment of the invention a circuit that is to be coupled to a reference voltage line. The circuit includes a noise coupling circuit that is to couple noise from the circuit to a reference voltage line based upon whether a driver is driving a data line.

Method To Reduce Timing Skews In I/O Circuits And Clock Drivers Caused By Fabrication Process Tolerances

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US Patent:
6480059, Nov 12, 2002
Filed:
Dec 28, 1999
Appl. No.:
09/473855
Inventors:
Sanjay Dabral - Milpitas CA
Krishna Seshan - San Jose CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 2500
US Classification:
327565, 257401
Abstract:
A method of reducing random, processing-induced timing variations in a field effect transistor device includes providing a semiconductor substrate having an active area, and forming a transistor having a gate over a portion of the active area, the gate having a first leg and a second leg. In a further aspect, a method of improving the timing skew of critically-matched circuits is presented. In a still further aspect of the invention, a field effect transistor and an integrated circuit device that can be used to improve timing robustness in the presence of random fabrication- or process-induced variations are presented.

Isbn (Books And Publications)

Basic Esd and I/O Design

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Author

Sanjay Dabral

ISBN #

0471253596

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Sanjay Dabral from Cupertino, CA, age ~59 Get Report