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Sanjay K Charagulla

from San Jose, CA
Age ~56
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Also known as:
Sanjay Kumar Charagulla, Sanjay Te Charagulla, Charagulla Sanjay Kumar, Sanjay A
Phone and address:
3283 Brittany Ct, San Jose, CA 95135
(408) 223-8764
Related to:
Kumarbabu K Obla, 57Sarita KumarShara N Kumar, 43Kumar Sivakumar Sharan, 43Mohit Kumar, 35Alok Kumar, 54Ayesha Charagulla, 48
Connected to:
Deepika Charagundla, 42Andreas C Charalambides, 48Charalampos Charalampous, 39Donna M Charalambous, 65George E Charalambous, 48Joanna Charalambous, 41Niki Charalambous, 61Salomi T Charalambous, 70Akshay P Charan, 34Deborah K Charan, 59

Sanjay Charagulla Phones & Addresses

  • 3283 Brittany Ct, San Jose, CA 95135 (408) 223-8764 (408) 799-0947
  • 7719 Snowy Egret Ct NW, Albuquerque, NM 87114
  • 1621 Warburton Ave, Santa Clara, CA 95050 (408) 249-3524
  • Edison, NJ
  • Stillwater, OK
  • Sunnyvale, CA

Public records

Vehicle Records

Sanjay Charagulla

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Address:
3283 Brittany Ct, San Jose, CA 95135
VIN:
4JGCB65E27A042894
Make:
MERCEDES-BENZ
Model:
R-CLASS
Year:
2007

Resumes

Resumes

Sanjay Charagulla Photo 1

Marketing And Strategy Executive

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Position:
Sr Director, Communications Business Strategy and Development at Xilinx
Location:
San Jose, California
Industry:
Semiconductors
Work:
Xilinx since Feb 2013
Sr Director, Communications Business Strategy and Development
Xilinx Nov 2010 - Feb 2013
Sr Director, Platform Solution Planning & Management
Xilinx Aug 2008 - Nov 2010
Director of Strategic Planning & Business Development
Altera corporation 2004 - Aug 2008
Sr Manager, Product Planning, Management & Marketing
Altera Corporation 2002 - 2004
System Architect
Education:
Nagarjuna University
BS EE, Electronics & Communications Oklahoma State University
MSEE, VLSI Stanford University Graduate School of Business
Skills:
Product Development
Architecture
Business Development
Strategy
Marketing
ASIC
Semiconductors
SoC
FPGA
IC
Verilog
EDA
Embedded Systems
Digital Signal Processors
Technical Marketing
Mixed Signal
Analog
Product Planning
Product Marketing
Product Management
Datacenter
CloudComputing
Server Storage
Interests:
job inquires, career opportunities, new ventures, professional networking, international travel, gourmet cooking, snow boarding, basketball, movies
Honor & Awards:
6 Patents awarded: Modular I/O bank architecture Embedded PCI-Express with programmable Chip DQS Post-amble Filtering for DDR2 DRAM Memories PCI Express hard-coded Transceiver solution Enhanced DLL phase output scheme Dynamic On-chip Termination Techniques
Sanjay Charagulla Photo 2

Advisory Board Member

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Location:
San Francisco, CA
Industry:
Semiconductors
Work:
Rutgers University
Advisory Board Member
Rambus
Vice President, Strategy, Sales, and Business Development
Globalfoundries
Senior Director, - Ai Accelerators, Data Center, Infrastructure, and Cryptocurrency
Xilinx Jan 2013 - Apr 2015
Senior Director, Business Management, Wired and Datacenter
Empower and Excel Jan 2013 - Apr 2015
Board Member
Education:
Stanford University Graduate School of Business
Master of Business Administration, Masters Nagarjuna University
Bachelors, Bachelor of Science, Electronics, Communications Oklahoma State University
Masters, Master of Science In Electrical Engineering
Skills:
Semiconductors
Asic
Product Management
Fpga
Embedded Systems
Soc
Cross Functional Team Leadership
Product Marketing
Ic
Field Programmable Gate Arrays
Strategy
Eda
System Architecture
Mixed Signal
Management
Application Specific Integrated Circuits
Product Development
Business Development
Processors
Product Planning
System on A Chip
Wireless
Competitive Analysis
Cloud Computing
Data Center
Technical Marketing
Analog
Verilog
Marketing
Start Ups
Digital Signal Processors
Go To Market Strategy
Integrated Circuits
Wireless Technologies
Wireline Networking
Architecture
Corporate Development
Server Storage
Interests:
Social Services
Children
Education
Poverty Alleviation
Science and Technology
Languages:
English
Hindi
Telugu

Business Records

Name / Title
Company / Classification
Phones & Addresses
Sanjay Charagulla
President
ALPHATECH SERVICES, INC
3283 Brittany Ct, San Jose, CA 95135

Publications

Us Patents

Implementation Of Pci Express

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US Patent:
7152136, Dec 19, 2006
Filed:
Aug 3, 2004
Appl. No.:
10/911212
Inventors:
Sanjay Charagulla - San Jose CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G06F 13/14
G06F 13/12
H04J 3/16
US Classification:
710315, 710305, 710 72, 710 62, 711103, 370469
Abstract:
Methods and apparatus are provided for providing PCI Express support. A device includes a hard-coded transceiver configured to support protocols such as Fibre Channel and the 10 Gigabit Attachment Unit Interface (XAUI), but the transceiver does not fully support PCI Express. Interface circuitry is configured to supplement or replace hard-coded transceiver components to provide PCI Express support. Interface circuitry allows PCI Express cores to operate with the transceiver that does not fully support PCI Express.

Embedded Pci-Express Implementation

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US Patent:
7257655, Aug 14, 2007
Filed:
Oct 13, 2004
Appl. No.:
10/964979
Inventors:
Ali H. Burney - Fremont CA, US
Sanjay Charagulla - San Jose CA, US
Daniel Mansur - Emerald Hills CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G06F 13/42
G06F 12/00
H04K 1/00
US Classification:
710105, 710 62, 710 72, 710305, 710315, 710260, 370436, 370469, 370408, 380268, 711103
Abstract:
Methods and apparatus provide PCI Express support on a programmable device. A device includes a hard-coded transceiver that supports functionality associated with the PCI Express physical layer and link layer. The hard-coded transceiver can also support part of the PCI Express transaction layer. Soft-coded logic is used to support higher layer functionality including a portion of the transaction layer to allow custom configuration of PCI Express features such as virtual channels, buffers, prioritization, and quality of service characteristics. The hybrid solution reduces logic resource cost and provides an effective custom configurable solution.

Enhanced Dll Phase Output Scheme

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US Patent:
7282973, Oct 16, 2007
Filed:
Dec 7, 2005
Appl. No.:
11/297040
Inventors:
Sanjay K. Charagulla - San Jose CA, US
Ali H. Burney - Fremont CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H03L 7/06
US Classification:
327158, 327159, 327161
Abstract:
A method and system using a delay-locked loop (DLL) to provide multiple phase locked outputs in discrete phase intervals is disclosed. In one embodiment, a reference clock signal is transmitted through a delay chain having a plurality of delay elements. The delay chain is capable of generating a plurality of output clock signals from the reference clock signal. Each of the output clock signals are delayed in discrete phase shift intervals with respect the delay elements. A first of the output clock signals and the reference clock signal are coupled to a first phase comparator capable of forming a first DLL with the delay chain. A second of the output clock signals and the reference clock signal are coupled to a second phase comparator capable of forming a second DLL with the delay chain. The output clock signal from the first DLL or the second DLL may be programmatically selected.

Dqs Postamble Filtering

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US Patent:
7324405, Jan 29, 2008
Filed:
Mar 3, 2006
Appl. No.:
11/368369
Inventors:
Sanjay K. Charagulla - San Jose CA, US
Chiakang Sung - Milpitas CA, US
Joseph Huang - San Jose CA, US
Bonnie I. Wang - Cupertino CA, US
Yan Chong - San Jose CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G11C 8/00
US Classification:
365233, 36518908, 365 63, 326 38, 327108
Abstract:
Circuits, methods, and apparatus for filtering signals at a high-speed data interface. One exemplary embodiment is particularly configured to filter a clock signal at the end of a data burst received by a double-data rate memory interface. A clock input port is either connected or disconnected to an input cell. When a data burst is to be received, the clock input port is connected to the input cell. When the data burst concludes, the clock input port is disconnected from the input cell. In a specific embodiment, a signal is received indicating that a data burst is about to begin and the clock input port is connected to the input cell. The signal later changes state indicating that the last data bit is being received. When the last clock edge corresponding to the last data bit is received, the clock input port is disconnected from the input cell.

Modular I/O Bank Architecture

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US Patent:
7378868, May 27, 2008
Filed:
Nov 9, 2006
Appl. No.:
11/558363
Inventors:
Jeffrey Tyhach - San Jose CA, US
Chiakang Sung - Milpitas CA, US
Khai Nguyen - San Jose CA, US
Sanjay K. Charagulla - San Jose CA, US
Ali Burney - Fremont CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H03K 19/173
US Classification:
326 38, 326 41
Abstract:
A programmable device I/O architecture allows for a variable number of I/O banks. Each I/O bank is of an I/O bank type. Each I/O bank type has a fixed number of I/O pins. I/O banks of the same I/O bank type are compatible within the same programmable device and between different types of programmable devices. The largest size I/O bank type and intermediate size I/O bank types are adapted to be a compatible supersets of every smaller I/O bank type. Support pins are regularly distributed between data pins in each I/O bank type. Multiple instances of the same or compatible I/O banks are arranged to be accessible from different sides of the programmable device. To facilitate circuit board layout, each I/O bank is arranged as a mirror and/or rotation of other I/O banks on the device.

Techniques For Providing Adjustable On-Chip Termination Impedance

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US Patent:
7417452, Aug 26, 2008
Filed:
Aug 5, 2006
Appl. No.:
11/462702
Inventors:
Xiaobao Wang - Cupertino CA, US
Chiakang Sung - Milpitas CA, US
Khai Q. Nguyen - San Jose CA, US
Sanjay K. Charagulla - San Jose CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H03K 17/16
H03K 19/003
US Classification:
326 30, 326 86, 326 87
Abstract:
Techniques are provided for individually adjusting the on-chip termination impedance that is generated by input and output (IO) buffers in an input/output (IO) bank on an integrated circuit. The IO buffers in an IO bank can generate different on-chip termination impedances. And as a result, an IO bank can support more than one class of memory interfaces. An OCT calibration block generates a digital on-chip termination (OCT) calibration code. In some embodiments, circuitry in the IO banks can be configured to shift the OCT calibration code by one or more bits to adjust the series and/or parallel on-chip termination impedance in one or more IO buffers.

Fully Buffered Dimm System And Method With Hard-Ip Memory Controller And Soft-Ip Frequency Controller

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US Patent:
7490209, Feb 10, 2009
Filed:
Dec 14, 2005
Appl. No.:
11/300812
Inventors:
Sanjay K. Charagulla - San Jose CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G06F 13/00
US Classification:
711167, 714 52, 714758
Abstract:
A system and method for memory control. The system includes a hard-IP memory controller, a soft-IP frequency conversion system, and an interface system. The soft-IP frequency conversion system is coupled to the hard-IP memory controller, and is capable of being programmed to convert data signals between a first frequency and a second frequency.

Programmable Logic Device Integrated Circuit With Dynamic Phase Alignment Capabilities And Shared Phase-Locked-Loop Circuitry

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US Patent:
7555667, Jun 30, 2009
Filed:
Jul 17, 2006
Appl. No.:
11/488365
Inventors:
Ali Burney - Fremont CA, US
Yu Xu - Palo Alto CA, US
Leon Zheng - Santa Clara CA, US
Sanjay K. Charagulla - San Jose CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G06F 1/04
G06F 1/06
US Classification:
713401, 713501, 713503
Abstract:
Adjustable transceiver circuitry is provided for programmable integrated circuits. The transceiver circuitry has a dynamic phase alignment circuit that can be used for aligning clock and data signals. The transceiver circuitry supports a phase-locked-loop source synchronous mode that can be used to receive data from transmitting integrated circuits that are clocked with a common clock. Each transmitting integrated circuit transmits a clock and associated data signals over a bus. The transceiver circuitry uses a master-slave architecture. A master dynamic phase alignment circuit in each transceiver receives the clock for that bus and selects a corresponding optimal clock phase to use in receiving input data for the bus from a multiphase clock. The master dynamic phase alignment circuit in each transceiver distributes the optimal clock phase to associated slave dynamic phase alignment circuits. Only a single phase-locked loop circuit is need to generate the multiphase clock.
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Sanjay K Charagulla from San Jose, CA, age ~56 Get Report