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Sajjad Ibrahim Pagarkar

from San Diego, CA
Age ~56

Sajjad Pagarkar Phones & Addresses

  • 13879 Torrey Bella Ct, San Diego, CA 92129
  • 10985 Guadalimar Way, San Diego, CA 92129 (858) 672-1721 (858) 672-5613
  • Beaverton, OR
  • Portland, OR

Work

Company: Qualcomm Apr 2010 Position: Principal engineer, manager

Education

Degree: MS ECE School / High School: Portland State University 1998 to 1999 Specialities: Electrical and Computer Engineering

Industries

Electrical/Electronic Manufacturing

Resumes

Resumes

Sajjad Pagarkar Photo 1

Principal Engineer, Manager At Qualcomm

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Position:
Principal Engineer, Manager at Qualcomm
Location:
Greater San Diego Area
Industry:
Electrical/Electronic Manufacturing
Work:
Qualcomm since Apr 2010
Principal Engineer, Manager

Qualcomm Jan 2006 - Apr 2010
Senior Staff Manager, Engineer
Education:
Portland State University 1998 - 1999
MS ECE, Electrical and Computer Engineering
University of Mumbai 1987 - 1991
BE, Elecronics Engineering
University of Mumbai 1987 - 1990
BS-Electronics Engineering, Eelctronics Engineering

Business Records

Name / Title
Company / Classification
Phones & Addresses
Sajjad Pagarkar
Bismillah Kabob-N-Curry LLC
Fine Dining Restaurant
5440 Clairemont Mesa Blvd, San Diego, CA 92117
10985 Guadalimar Way, San Diego, CA 92129
Sajjad Pagarkar
Principal
Smart Groceries LLC
Ret Groceries · Retail Grocery Market
5440 Clairemont Mesa Blvd, San Diego, CA 92117
12320 Colony Dr, Poway, CA 92064

Publications

Us Patents

Method And Apparatus For High Volume System Level Testing Of Logic Devices With Pop Memory

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US Patent:
20140361800, Dec 11, 2014
Filed:
Jan 13, 2014
Appl. No.:
14/154064
Inventors:
- San Diego CA, US
Rae-Ann S. LoCicero - La Jolla CA, US
Michael A. Monroe - Poway CA, US
Anthony T. Newman - San Diego CA, US
Nathan M. Luke - San Diego CA, US
Fadi G. Kanj - Escondido CA, US
Sajjad I. Pagarkar - San Diego CA, US
Jatin N. Patel - San Diego CA, US
Assignee:
Qualcomm Incorporated - San Diego CA
International Classification:
G01R 31/28
US Classification:
32475025
Abstract:
A method and apparatus for high volume testing of logic devices with package-on-package (POP) memory. The apparatus includes a handler arm, compound nest attached to the handler arm, swing arm and a socketed assembly that facilitates alignment. In the method, a logic device is first installed in a compound nest. The compound nest is them attached to a handler arm. The compound nest is then aligned with a socketed assembly using a swing arm. Fine tuning of the alignment may be performed using guide pins and shoulder screws.

Method For Performing Adaptive Voltage Scaling (Avs) And Integrated Circuit Configured To Perform Avs

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US Patent:
20140191794, Jul 10, 2014
Filed:
Jan 8, 2013
Appl. No.:
13/736295
Inventors:
- San Diego CA, US
Stephen Simmonds - San Diego CA, US
Parag Arun Agashe - San Diego CA, US
Sajjad Pagarkar - San Diego CA, US
Ashwin Rabindranath - San Diego CA, US
Sagar Digwalekar - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
G05F 1/10
US Classification:
327513, 327540
Abstract:
An integrated circuit (IC) includes an adaptive voltage scaling (AVS) controller configured to control a voltage supplied to a portion of the IC and at least one sensor configured to sense at least one state of the IC and to provide an output signal indicative of the at least one sensed state to the AVS controller, the IC having a first setting and a second setting, the AVS controller being configured to use the output signal to control the voltage in the first setting and the AVS controller being configured to control the voltage independently of the output signal in the second setting. Also a method of performing AVS is provided.
Sajjad Ibrahim Pagarkar from San Diego, CA, age ~56 Get Report