Sachidanandan Sambandan

6374326, Apr 16, 2002

Oct 25, 1999

09/426574

Arvind K. Kansal - Cupertino CA
Mark A. Ross - San Carlos CA
Sachidanandan Sambandan - Sunnyvale CA

Cisco Technology, Inc. - San Jose CA

G06F 1200

711108, 711 5, 711168, 365 49, 36523003, 370392

Content-addressable memory (CAM) architectures and methods of use are disclosed for enabling multiple concurrent lookups within a CAM array. One implementation arranges CAM arrays into multiple banks and enables parallel lookups of multiple key strings in multiple CAM banks. For a given input key, simultaneous parallel lookups in a plurality of CAM banks are performed by each bank using a bank key consisting of a subset of the bits of the input key. The multiple bank CAM is instructed to extract one or more distinct subsets of input key bits for use as bank lookup keys. Each bank key is passed to the appropriate bank according to the instruction received. Multiple bank sizes, depending on the key width and overall size of the CAM array, are also possible. Each bank produces a single output result, and each bank is returned to the host device that initially issued the lookup instruction.

6385688, May 7, 2002

Jun 18, 1997

08/877840

Duane R. Mills - Folsom CA
Brian Lyn Dipert - Sacramento CA
Sachidanandan Sambandan - Folsom CA
Bruce McCormick - Roseville CA
Richard D. Pashley - Roseville CA

Intel Corporation - Santa Clara CA

G06F 1200

711103, 711100, 711101, 711102, 711104

A flash memory chip that can be switched into four different read modes is described. In asynchronous flash mode, the flash memory is read as a standard flash memory. In synchronous flash mode, a clock signal is provided to the flash chip and a series of addresses belonging to a data burst are specified, one address per clock period. The data stored at the specified addresses are output sequentially during subsequent clock periods. In asynchronous DRAM mode, the flash memory emulates DRAM. In synchronous DRAM mode, the flash memory emulates synchronous DRAM.

6564285, May 13, 2003

Jun 14, 2000

09/595327

Duane R. Mills - Folsom CA
Brian Lyn Dipert - Sacramento CA
Sachidanandan Sambandan - Folsom CA
Bruce McCormick - Roseville CA
Richard D. Pashley - Roseville CA

Intel Corporation - Santa Clara CA

G06F 1200

711103, 711101, 711102, 711167, 711168, 711169

A flash memory chip that can be switched into four different read modes is described. In asynchronous flash mode, the flash memory is read as a standard flash memory. In synchronous flash mode, a clock signal is provided to the flash chip and a series of addresses belonging to a data burst are specified, one address per clock period. The data stored at the specified addresses are output sequentially during subsequent clock periods. In asynchronous DRAM mode, the flash memory emulates DRAM. In synchronous DRAM mode the flash memory emulates synchronous DRAM.

60264659, Feb 15, 2000

Jun 18, 1997

8/897499

Duane R. Mills - Folsom CA
Brian Lyn Dipert - Sacramento CA
Sachidanandan Sambandan - Folsom CA
Bruce McCormick - Roseville CA
Richard D. Pashley - Roseville CA

Intel Corporation - Santa Clara CA

G06F 1316
G06F 1200

711103

A flash memory chip that can be switched into four different read modes is described. In the first read mode, asynchronous flash mode, the flash memory is read as a standard flash memory where the reading of the contents of a first address must be completed before a second address to be read can be specified. In the second read mode, synchronous flash mode, a clock signal is provided to the flash chip and a series of addresses belonging to a data burst are specified, one address per clock tick. Then, the contents stored at the addresses specified for the burst are output sequentially during subsequent clock ticks in the order in which the addresses were provided. Alternately, if a single address is provided to the flash chip when it is in the synchronous mode, the subsequent addresses for the burst will be generated within the flash chip and the data burst will then be provided as output from the flash chip. In the third read mode, asynchronous DRAM mode, the row and column addresses are strobed into the flash memory using strobe signals. The flash memory then converts the row and column addresses internally into a single address and provides as output the data stored at that single address.

56969171, Dec 9, 1997

Jun 3, 1994

8/253499

Duane R. Mills - Folsom CA
Brian Lyn Dipert - Sacramento CA
Sachidanandan Sambandan - Folsom CA
Bruce McCormick - Granite Bay CA
Richard D. Pashley - Roseville CA

Intel Corporation - Santa Clara CA

G06F 1200

395401

An asynchronous nonvolatile memory includes a plurality of individual memory components. A burst read operation references consecutive addresses beginning with a first address, wherein the consecutive addresses are not located in a same memory component. A method of performing a burst read operation in the asynchronous nonvolatile memory includes the step of providing the first address as a current address to the plurality of individual components. A current page identified by m higher order bits of the current address is selected. Each of the individual memory components senses a location identified by the m higher order bits. An output of a selected individual memory component is enabled in accordance with n lower bits of the current address. A consecutive subsequent address is provided, wherein the current address becomes a preceding address and the consecutive subsequent address becomes the current address. The output of another selected individual memory component identified by the n lower order bits of the current address is enabled without generating wait states, if the current and preceding addresses identify a same page.

52894126, Feb 22, 1994

Jun 19, 1992

7/901395

Kevin W. Frary - Fair Oaks CA
Sachidanandan Sambandan - Folsom CA

Intel Corporation - Santa Clara CA

G11C 700

365185

A circuit for providing reference voltages to be used by sense amplifiers of output circuitry of an integrated circuit memory array to allow the sense amplifiers to ascertain the values stored by memory cells of the array. The circuit includes a first branch which has transistor circuitry for establishing a reference current, a second branch of the circuit including a first transistor device and apparatus for mirroring the reference current through the first transistor device, and a plurality of output branches each connected to a sense amplifier to provide a reference voltage to be used by the sense amplifier. Each of the output branches includes a second transistor device with characteristics essentially identical to the characteristics of the first transistor device. Apparatus is included in the output branches for providing voltages at all terminals of the second transistor devices equal to the voltages at all terminals of the first transistor device so that the reference current through each of the second transistor devices is forced to be identical to that through the first transistor device. The second branch is replicated to increase current available and circuit speed.

53474848, Sep 13, 1994

Mar 23, 1994

8/216766

Phillip M. Kwong - Folsom CA
Sachidanandan Sambandan - Folsom CA
Sherif R. B. Sweha - El Dorado Hills CA
Duane R. Mills - Folsom CA

Intel Corporation - Santa Clara CA

G11C 1140

365 49

A nonvolatile memory device is described. The memory device includes a main memory array for storing data. The main memory array comprises a first block and a second block. A redundant memory array comprises a first redundant block and a second redundant block. The first redundant block comprises a first redundant column of memory cells and a second redundant column of memory cells. The second redundant block comprises a third redundant column of memory cells and a fourth redundant column of memory cells. A content addressable memory (CAM) comprises a first set of CAM cells for storing a first address of a first defective column in the main memory array and a second set of CAM cells for storing a second address of a second defective column in the main memory array. The first set of CAM cells cause the first redundant column in the first redundant block to replace the first defective column when the first defective column is in the first block. The first set of CAM cells cause the third redundant column in the second redundant block to replace the first defective column when the first defective column is in the second block.

59266511, Jul 20, 1999

Jul 28, 1995

8/508668

Robert J. Johnston - Fair Oaks CA
Tuong Trieu - Folsom CA
Sachidanandan Sambandan - Folsom CA

Intel Corporation - Santa Clara CA

G06F 1300

395872

An output buffer circuit including different arrangements of output devices selectable by circuitry which tests the load characteristics to provide different buffer drive strengths, and different paths having different current carrying characteristics for enabling the output devices selectable by the circuitry which tests the load characteristics to vary the slew rate of the output devices to best match the load.