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Rui M Bastos

from San Jose, CA
Age ~58
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Related to:
Claudine C Bastos, 56Claudine C Bastos
Connected to:
Alfredo S Bastos, 60Branden A Bastos, 38Darcy C Bastos, 52Dominique Bastos, 56Emmanuel D Bastos, 58Erica S Bastos, 32Helena A Bastos, 77Jessie K Bastos, 45Mauricio Bastos, 42Micaela P Bastos, 35

Rui Bastos Phones & Addresses

  • 1930 Almaden Rd APT 114, San Jose, CA 95125
  • 2250 Monroe St, Santa Clara, CA 95050 (408) 243-4921 (408) 241-6611 (408) 983-0912
  • Chapel Hill, NC
  • Mountain View, CA
  • Breese, IL
  • 2250 Monroe St APT 235, Santa Clara, CA 95050 (408) 710-2077

Work

Position: Administrative Support Occupations, Including Clerical Occupations

Education

Degree: High school graduate or higher

Resumes

Resumes

Rui Bastos Photo 1

3D Graphics Architect

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Location:
San Francisco, CA
Industry:
Computer Hardware
Work:
Discreet Logic Autodesk Canada 1998 - 1998
Intern
Nvidia 1998 - 1998
3D Graphics Architect
Education:
University of North Carolina at Chapel Hill
Faculdade De Ciências Econômicas | Ufrgs
Skills:
Gpu
Computer Architecture
Cuda
Computer Graphics
Gpgpu
Opengl
Processors
Debugging
Parallel Computing
Microprocessors
Algorithms
High Performance Computing
Verilog
Soc
Device Drivers
Parallel Programming
Asic
Direct3D
Directx
Rui Bastos Photo 2

Rui Bastos

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Rui Bastos Photo 3

Rui Bastos

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Rui Bastos Photo 4

Rui Bastos

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Rui Bastos Photo 5

Rui Bastos

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Location:
Estados Unidos

Publications

Us Patents

System And Method For Using And Collecting Information From A Plurality Of Depth Layers

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US Patent:
6744433, Jun 1, 2004
Filed:
Aug 31, 2001
Appl. No.:
09/945444
Inventors:
Rui M. Bastos - Santa Clara CA
Cass W. Everitt - Pflugerville TX
Mark J. Kilgard - Austin TX
Assignee:
nVidia Corporation - Santa Clara CA
International Classification:
G06T 1540
US Classification:
345422, 345426, 345581, 345582, 345506
Abstract:
A system and method are provided for using information from at least one depth layer and for collecting information about at least one additional depth layer utilizing a graphics pipeline. Initially, constraining depth layers are provided which, in turn, define a plurality of depth constraints. Next, a plurality of tests is performed involving the constraining depth layers for collecting information about at least one additional depth layer. The information relating to the at least one depth layer may then be used to improve processing in the graphics pipeline. By the foregoing multiple tests, information relating to a plurality of depth layers may be collected during each of a plurality of rendering passes. Initially, information relating to the constraining depth layers and associated depth constraints is provided in the aforementioned manner. Thereafter, information relating to at least one additional depth layer is collected during additional rendering passes using multiple tests on each rendering pass.

Antialiasing Using Hybrid Supersampling-Multisampling

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US Patent:
6967663, Nov 22, 2005
Filed:
Sep 8, 2003
Appl. No.:
10/658056
Inventors:
Rui M. Bastos - Santa Clara CA, US
Steven E. Molnar - Chapel Hill NC, US
Michael J. M. Toksvig - Palo Alto CA, US
Matthew J. Craighead - Santa Clara CA, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G09G005/00
G06T015/50
US Classification:
345613, 345426
Abstract:
Hybrid sampling of pixels of an image involves generating shading values at multiple shading sample locations and generating depth values at multiple depth sample locations, with the number of depth sample locations exceeding the number of shading sample locations. Each shading sample location is associated with one or more of the depth sample locations. Generation and filtering of hybrid sampled pixel data can be done within a graphics processing system, transparent to an application that provides image data.

Depth-Of-Field Effects Using Texture Lookup

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US Patent:
6975329, Dec 13, 2005
Filed:
Dec 9, 2002
Appl. No.:
10/314877
Inventors:
Rui M. Bastos - Santa Clara CA, US
Stephen D. Lew - Sunnyvale CA, US
Curtis A. Beeson - Fremont CA, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G09G005/00
G06T015/40
US Classification:
345587, 345422
Abstract:
A graphical processing unit (GPU) and methods for rendering a three-dimensional (3D) scene generated in a field of view having in-focus and out-of-focus regions on a two-dimensional (2D) screen region of pixels are described. One method includes initially rendering the scene to create color and depth texture maps and creating mip-map layers for the color texture map. The method further comprises subsequently rendering the scene by, for each pixel: creating a mip-map layer selection value as a function of a depth of the pixel from the depth texture map, generating a color value by interpolation using color values from at least one of the mip-map layers chosen according to the mip-map layer selection value, and setting a color of the pixel to the generated color texture.

Shader Pixel Storage In A Graphics Memory

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US Patent:
6985151, Jan 10, 2006
Filed:
Jan 6, 2004
Appl. No.:
10/752783
Inventors:
Rui M. Bastos - Santa Clara CA, US
Walter E. Donovan - Saratoga CA, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G06F 15/76
US Classification:
345519, 345531, 345552, 345557, 345522
Abstract:
Circuits, apparatus, and methods that enable a shader to read and write data from and to a memory location during a single pass through a graphics pipeline. Some embodiments of the present invention provide an increase in the number of buffers available to a shader. These buffers may be read/write (input/output) or read only (input) buffers. Another provides pixel store and pixel load commands that may be used as instructions in a shader program or program portion, and may appear at positions other than the end of the shader program or program portion. Other embodiments provide a data path between a shader and a graphics memory, typically through a frame buffer interface. This data path simplifies the timing of the above store (write) and load (read) commands. Various embodiments may incorporate one or more of these features.

Order-Independent Transparency Rendering System And Method

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US Patent:
6989840, Jan 24, 2006
Filed:
Aug 31, 2001
Appl. No.:
09/944988
Inventors:
Cass W. Everitt - Pflugerville TX, US
Rui M. Bastos - Santa Clara CA, US
Mark J. Kilgard - Austin TX, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G09G 5/02
US Classification:
345592, 345422, 345581
Abstract:
A system, method and computer program product are provided for transparency rendering in a graphics pipeline. Initially, colored-transparency information is collected from a plurality of depth layers (i. e. colored-transparency layers, etc. ) in a scene to be rendered. The collected colored-transparency information is then stored in memory. The colored-transparency information from the depth layers may then be blended in a predetermined order.

Method And Apparatus For Multithreaded Processing Of Data In A Programmable Graphics Processor

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US Patent:
7015913, Mar 21, 2006
Filed:
Jun 27, 2003
Appl. No.:
10/608346
Inventors:
John Erik Lindholm - Saratoga CA, US
Rui M. Bastos - Santa Clara CA, US
Harold Robert Feldman Zatz - Palo Alto CA, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G06F 15/00
G06F 12/02
G06F 9/46
G06T 1/00
US Classification:
345501, 345543, 718102, 718104
Abstract:
A graphics processor and method for executing a graphics program as a plurality of threads where each sample to be processed by the program is assigned to a thread. Although threads share processing resources within the programmable graphics processor, the execution of each thread can proceed independent of any other threads. For example, instructions in a second thread are scheduled for execution while execution of instructions in a first thread are stalled waiting for source data. Consequently, a first received sample (assigned to the first thread) may be processed after a second received sample (assigned to the second thread). A benefit of independently executing each thread is improved performance because a stalled thread does not prevent the execution of other threads.

Multiple Data Buffers For Processing Graphics Data

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US Patent:
7015914, Mar 21, 2006
Filed:
Dec 10, 2003
Appl. No.:
10/732730
Inventors:
Rui M. Bastos - Santa Clara CA, US
Matthew N. Papakipos - Palo Alto CA, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G06T 1/20
G09G 5/36
US Classification:
345506, 345531
Abstract:
Multiple output buffers are supported in a graphics processor. Each output buffer has a unique identifier and may include data represented in a variety of fixed and floating-point formats (8-bit, 16-bit, 32-bit, 64-bit and higher). A fragment program executed by the graphics processor can access (read or write any of the output buffers. Each of the output buffers may be read from and used to process graphics data by a fragment shader within the graphics processor. Likewise, each output buffer may be written to by the graphics processor, storing graphics data such as lighting parameters, indices, color, and depth.

Generation Of Jittered Sub-Pixel Samples Using Programmable Sub-Pixel Offsets

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US Patent:
7050068, May 23, 2006
Filed:
Dec 2, 2003
Appl. No.:
10/726125
Inventors:
Rui M. Bastos - Santa Clara CA, US
Nathan A. Carr - Urbana IL, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G09G 5/00
US Classification:
345613, 345611, 345614
Abstract:
Jittered sub-pixel samples are used to reduce aliasing during rendering in a graphics pipeline. Sub-pixel samples are jittered using programmed sub-pixel offset values, permitting an application to select not only the number of sub-pixel samples within a pixel, but also the position of each sub-pixel sample within the pixel.
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Rui M Bastos from San Jose, CA, age ~58 Get Report