Roy C Flaker

8093657, Jan 10, 2012

Jul 28, 2008

12/181007

Roy Childs Flaker - Essex Junction VT, US
Catherine O'Brien, legal representative - Essex Junction VT, US
Scott Flaker, legal representative - Essex Junction VT, US
Bruce Flaker, legal representative - Essex Junction VT, US
Anne Flaker, legal representative - Essex Junction VT, US
Heather Flaker, legal representative - Essex Junction VT, US
Louis C. Hsu - Fishkill NY, US
Jente Kuang - Poughkeepsie NY, US

International Business Machines Corporation - Armonk NY

H01L 27/13

257350, 257353, 257E27112

According to the present invention, a circuit and methods for enhancing the operation of SOI fabricated devices are disclosed. In a preferred embodiment of the present invention, a pulse discharge circuit is provided. Here, a circuit is designed to provide a pulse that will discharge the accumulated electrical charge on the body of the SOI devices in the memory subarray just prior to the first access cycle. As explained above, once the accumulated charge has been dissipated, the speed penalty for successive accesses to the memory subarray is eliminated or greatly reduced. With a proper control signal, timing and sizing, this can be a very effective method to solve the problem associated with the SOI loading effect. Alternatively, instead of connecting the bodies of all SOI devices in a memory circuit to ground, the bodies of the N-channel FET pull-down devices of the local word line drivers can be selectively connected to a reference ground. This would enable the circuit to retain most of the speed advantages associated with SOI devices while overcoming the loading problem described above.

56045182, Feb 18, 1997

Mar 30, 1994

8/220090

Roy C. Flaker - Essex Junction VT
Gregory J. Schroer - Essex Junction VT
Roderick M. P. West - Colchester VT
Todd Williams - Burlington VT

International Business Machines Corporation - Armonk NY

G09G 506

345199

An integrated memory structure, and associated processing method, is coupled to receive address data and control data. The memory structure includes a composite memory array having a first array portion and a second array portion which are separately addressable. The first array portion is accessed using at least some of the address data as a first address signal and the second array portion is addressed using at least some of the control data also as a second address signal. The memory structure is presented herein by way of example for a serial palette digital-to-analog (SPD) device, and incorporates indirect color mode, direct color mode, overlay color mode and cursor color mode processing in a single macro. When in direct color mode, access to the memory array is disabled and address data is transferred directly to an output of the memory structure as data out.

57400989, Apr 14, 1998

Jun 27, 1996

8/671279

Robert Dean Adams - Essex Junction VT
John Connor - Burlington VT
James J. Covino - Essex Junction VT
Roy Childs Flaker - Essex Junction VT
Garrett Stephen Koch - Cambridge VT
Alan Lee Roberts - Jericho VT
Jose Roriz Sousa - Colchester VT
Luigi Ternullo - Colchester VT

International Business Machines Corporation - Armonk NY

G11C 1500

365 49

An associated memory structure having a plurality of memories amenable for testing and a method of testing the memories is provided. First and second memories are formed, wherein data in the first memory provides a basis for at least a portion of the input to the second memory during functional operation of two memories. Preferably, an output latch for receiving the output test data from the first memory is provided. Means are provided for loading the first memory with data which is utilized as a basis for providing at least a portion of the input to the second memory. An access path from the output port of the first memory to the input port of the second memory allows use of the data in the first memory to generate at least a portion of the input to the second memory. The first memory is first tested independently of the second memory. Thereafter, the first memory is loaded with preconditioned data that is used as a basis for inputs to the second memory during testing of the second memory.

55921426, Jan 7, 1997

Sep 15, 1995

8/529255

R. Dean Adams - Essex Junction VT
Donald A. Evans - Williston VT
Roy C. Flaker - Essex Junction VT

International Business Machines Corporation - Armonk NY

G06F 702

3401462

The high speed greater than or equal to compare circuit comprises an equal to compare circuit having M number of exclusive-OR gates input into a NOR gate, each exclusive-OR gate N of the M number of exclusive-OR gates receiving as inputs a Nth bit of a first digital number having M bits and a corresponding Nth bit of a second digital number having M bits, wherein 1

55638333, Oct 8, 1996

Mar 3, 1995

8/398465

Robert D. Adams - Essex Junction VT
John Connor - Burlington VT
James J. Covino - Essex Junction VT
Roy C. Flaker - Essex Junction VT
Garrett S. Koch - Cambridge VT
Alan L. Roberts - Jericho VT
Jose R. Sousa - Colchester VT
Luigi Ternullo - Colchester VT

International Business Machines Corporation - Armonk NY

G11C 700

365201

An associated memory structure having a plurality of memories amenable for testing and a method of testing the memories is provided. First and second memories are formed, wherein data in the first memory provides a basis for at least a portion of the input to the second memory during functional operation of two memories. Preferably, an output latch for receiving the output test data from the first memory is provided. Means are provided for loading the first memory with data which is utilized as a basis for providing at least a portion of the input to the second memory. An access path from the output port of the first memory to the input port of the second memory allows use of the data in the first memory to generate at least a portion of the input to the second memory. The first memory is first tested independently of the second memory. Thereafter, the first memory is loaded with preconditioned data that is used as a basis for inputs to the second memory during testing of the second memory.

57218633, Feb 24, 1998

Jan 29, 1996

8/593639

James J. Covino - Essex Junction VT
Roy Childs Flaker - Essex Junction VT
Alan Lee Roberts - Jericho VT
Jose Roriz Sousa - Colchester VT

International Business Machines Corporation - Armonk NY

G06F 1208

395455

A structure and method of operation of a cache memory are provided. The cache memory is organized such that the data on a given line of any page of the main memory is stored on the same line of a page of the cache memory. Two address memories are provided, one containing the first eight bits of the virtual address of the page of the data in main memory and the second the entire real page address in main memory. When an address is asserted on the bus, the line component of the address causes each of those lines from the cache memory to read out to a multiplexor. At the same time, the eight bit component of the virtual address is compared in the first memory to the eight bits of each line stored in the first memory, and if a compare is made, the data on that line from that page of cache memory is read to the CPU. Also, the entire real address is compared in the second memory, and if a match does not occur, the data from the cache to the CPU is flagged as invalid data. A structure and method are also provided to determine if duplicate addresses exist in the second address memory.

47301228, Mar 8, 1988

Sep 18, 1986

6/908846

Jeffrey H. Dreibelbis - Williston VT
Roy C. Flaker - Essex Junction VT
Erik L. Hedberg - Essex Center VT

International Business Machines Corporation - Armonk NY

H02J 304

307 75

A power supply adapter system is provided which includes a voltage supply source terminal, an output terminal, first and second switches, the first switch being disposed between the voltage supply source terminal and the output terminal, voltage conversion means serially connected with the second switch and disposed between the voltage supply source terminal and a point of reference potential and having an output coupled to the output terminal, and means for detecting first and second ranges of voltages at the power supply source terminal and for producing first and second control voltages, respectively, to control the first and second switches.

57151881, Feb 3, 1998

Feb 7, 1996

8/597773

James J. Covino - Essex Junction VT
Roy Childs Flaker - Essex Junction VT
Alan Lee Roberts - Jericho VT
Jose Roriz Sousa - Colchester VT

International Business Machines Corporation - Armonk NY

G11C 1300

365 49

A method and apparatus are provided for parallel addressing a CAM and a RAM, and also for using a single wordline to address the CAM and/or RAM. The CAM and RAM are addressed using a common wordline, and the common wordline is also used for writing to the CAM during a write cycle and strobing the CAM during a read cycle.