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Roman R Malendevich

from Sunnyvale, CA
Age ~53
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Also known as:
Roman Dr Malendevich, Roman H
Phone and address:
675 Tasman Dr APT 2314, Sunnyvale, CA 94089
Related to:
Carol I Mclaughlin, 71Kristin M Thornton, 45Saundra Thornton, 65Brian ThorntonJennifer Lloyd, 49Patricia Plattenburg, 71
Connected to:
Aaron M Malenfant, 32Angela L Malenfant, 67Christian W Malenfant, 67Dennis D Malenfant, 71Derek Malenfant, 55Eric Malenfant, 43Gregory T Malenfant, 32Marc W Malenfant, 50Diane M Malenke, 61Gail K Malenke, 74

Roman Malendevich Phones & Addresses

  • 675 Tasman Dr APT 2314, Sunnyvale, CA 94089
  • Oceanside, CA
  • Casselberry, FL
  • Orlando, FL
  • Pasadena, CA
  • Carlsbad, CA
  • San Diego, CA

Work

Company: Infinera 2006 Address: Sunnyvale CA Position: Principal engineer (optical system architecture and pic/modules)

Education

Degree: Ph.D. School / High School: University of Central Florida 2001 Specialities: Optics / CREOL

Skills

Optics • Optoelectronics • Photonics • Fiber Optics • Simulations • Testing • R&D • Optical Communications • Optical Fiber • Optical Engineering • Physics • Engineering Management • Semiconductors • Matlab • Labview

Interests

Economics and Communication

Industries

Telecommunications

Resumes

Resumes

Roman Malendevich Photo 1

Principal Engineer, Si Photonics

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Location:
1245 Lakeside Dr, Sunnyvale, CA 94085
Industry:
Telecommunications
Work:
Infinera - Sunnyvale CA since 2006
Principal Engineer (Optical System Architecture and PIC/Modules)
Luxtera, Inc - Carlsbad CA 2001 - 2006
Sr. Optical Designer & Test Team Lead
Education:
University of Central Florida 2001
Ph.D., Optics / CREOL Kiev National University 1996
M.S., Physics (minor in computer science)
Skills:
Optics
Optoelectronics
Photonics
Fiber Optics
Simulations
Testing
R&D
Optical Communications
Optical Fiber
Optical Engineering
Physics
Engineering Management
Semiconductors
Matlab
Labview
Interests:
Economics and Communication

Publications

Us Patents

Optical Probes With Spacing Sensors For The Wafer Level Testing Of Optical And Optoelectronic Chips

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US Patent:
7183759, Feb 27, 2007
Filed:
Dec 17, 2004
Appl. No.:
11/015981
Inventors:
Roman Malendevich - Oceanside CA, US
Myles Sussman - San Mateo CA, US
Assignee:
Luxtera, Inc. - Carlsbad CA
International Classification:
G01R 31/302
US Classification:
3241581, 324752, 324750
Abstract:
This application describes, among others, wafer designs, testing systems and techniques for wafer-level optical testing by coupling probe light to/from the top of the wafer. During the optical testing, the vertical spacing between an optical probe and the wafer is set to a very close distance, to achieve efficient optical coupling. It is beneficial to keep this close distance during optical testing as a constant in testing different optical components at different locations on the wafer. In one implementation, a spacing sensor may be used to measure the height of the optical probe from the wafer surface. This sensor may be a capacitance sensor that is mounted at the optical probe.

Wafer-Level Testing Of Optical And Optoelectronic Chips

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US Patent:
7184626, Feb 27, 2007
Filed:
Apr 7, 2004
Appl. No.:
10/820631
Inventors:
Roman Malendevich - Oceanside CA, US
Thierry J. Pinguet - Cardif-By-The-Sea CA, US
Maxime J. Rattier - Paris, FR
Myles Sussman - San Diego CA, US
Jeremy Witzens - Pasadena CA, US
Assignee:
Luxtera, Inc - Carlsbad CA
International Classification:
G02B 6/34
G01R 31/302
US Classification:
385 37, 324752
Abstract:
This application describes, among others, wafer designs, testing systems and techniques for wafer-level optical testing by coupling probe light from top of the wafer.

Optical Alignment Loops For The Wafer-Level Testing Of Optical And Optoelectronic Chips

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US Patent:
7224174, May 29, 2007
Filed:
Dec 17, 2004
Appl. No.:
11/015957
Inventors:
Roman Malendevich - Oceanside CA, US
Myles Sussman - San Mateo CA, US
Assignee:
Luxtera, Inc. - Carlsbad CA
International Classification:
G01R 31/02
US Classification:
324758
Abstract:
This application describes, among others, wafer designs, testing systems and techniques for wafer-level optical testing by coupling probe light to/from the top of the wafer. A wafer level test system uses an optical probe to search for and align with an optical alignment loop. The test system uses a located alignment loop as a reference point to locate other devices on the wafer. The test system tests the operation of selected devices disposed on the wafer. The alignment loop is also used as a reference device for an adjacent device of unknown performance.

Optoelectronic Alignment Structures For The Wafer Level Testing Of Optical And Optoelectronic Chips

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US Patent:
7298939, Nov 20, 2007
Filed:
Mar 16, 2005
Appl. No.:
11/083705
Inventors:
Roman Malendevich - Oceanside CA, US
Myles Sussman - San Mateo CA, US
Lawrence C. Gunn III - Encinitas CA, US
Assignee:
Luxtera, Inc. - Carlsbad CA
International Classification:
G02B 6/28
H01L 27/15
US Classification:
385 31, 257 82
Abstract:
This application describes, among others, wafer designs, testing systems and techniques for wafer-level optical testing by coupling probe light to/from the top of a wafer. A wafer level test system uses optical and electronic probes to search for and align with an optoelectronic alignment structure. The test system uses a located optoelectronic alignment structure as a reference point to locate other devices on the wafer. The system tests the operation of selected devices disposed on the wafer. The optoelectronic alignment loop is also used as an alignment reference of known performance for an adjacent device of unknown performance.

Optical Alignment Loops For The Wafer-Level Testing Of Optical And Optoelectronic Chips

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US Patent:
7378861, May 27, 2008
Filed:
Feb 26, 2007
Appl. No.:
11/711452
Inventors:
Roman Malendevich - Oceanside CA, US
Myles Sussman - San Mateo CA, US
Assignee:
Luxtera, Inc. - Carlsbad CA
International Classification:
G01R 31/02
US Classification:
324758
Abstract:
This application describes, among others, wafer designs, testing systems and techniques for wafer-level optical testing by coupling probe light to/from the top of the wafer. A wafer level test system uses an optical probe to search for and align with an optical alignment loop. The test system uses a located alignment loop as a reference point to locate other devices on the wafer. The test system tests the operation of selected devices disposed on the wafer. The alignment loop is also used as a reference device for an adjacent device of unknown performance.

Optoelectronic Alignment Structures For The Wafer Level Testing Of Optical And Optoelectronic Chips

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US Patent:
7412138, Aug 12, 2008
Filed:
Feb 28, 2007
Appl. No.:
11/713479
Inventors:
Roman Malendevich - Oceanside CA, US
Myles Sussman - San Mateo CA, US
Assignee:
Luxtera, Inc. - Carlsbad CA
International Classification:
G02B 6/26
US Classification:
385 52
Abstract:
This application describes, among others, wafer designs, testing systems and techniques for wafer-level optical testing by coupling probe light to/from the top of a wafer. A wafer level test system uses optical and electronic probes to search for and align with an optoelectronic alignment structure. The test system uses a located optoelectronic alignment structure as a reference point to locate other devices on the wafer. The system tests the operation of selected devices disposed on the wafer. The optoelectronic alignment loop is also used as an alignment reference of known performance for an adjacent device of unknown performance.

Wafer-Level Testing Of Optical And Optoelectronic Chips

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US Patent:
7586608, Sep 8, 2009
Filed:
Mar 28, 2007
Appl. No.:
11/729814
Inventors:
Roman Malendevich - Sunnyvale CA, US
Thierry J. Pinguet - Cardiff by the Sea CA, US
Maxime Jean Rattier - Paris, FR
Myles Sussman - San Mateo CA, US
Jeremy Witzens - Del Mar CA, US
Assignee:
Luxtera, Inc. - Carlsbad CA
International Classification:
G01B 11/00
G01N 21/00
G01N 21/55
G06K 9/00
H01L 21/00
G01R 31/26
H01L 21/66
G01N 21/86
G01V 8/00
US Classification:
356399, 3562374, 3562375, 356401, 356445, 382145, 438 7, 438 14, 438 16, 2505594
Abstract:
This application describes, among others, wafer designs, testing systems and techniques for wafer-level optical testing by coupling probe light from top of the wafer.

Wafer-Level Testing Of Optical And Optoelectronic Chips

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US Patent:
7262852, Aug 28, 2007
Filed:
Nov 14, 2005
Appl. No.:
11/273753
Inventors:
Roman Malendevich - Oceanside CA, US
Thierry J. Pinguet - Cardiff-By-The-Sea CA, US
Maxime Jean Rattier - Paris, FR
Myles Sussman - San Mateo CA, US
Jeremy Witzens - Pasadena CA, US
Assignee:
Luxtera, Inc. - Carlsbad CA
International Classification:
G01B 11/00
G01N 21/00
G01N 21/55
G01N 21/86
G06K 9/00
H01L 21/00
H01L 21/66
G01R 31/26
G01V 8/00
US Classification:
356401, 3562374, 3562375, 356445, 382145, 438 7, 438 14, 438 16, 2505594
Abstract:
This application describes, among others, wafer designs, testing systems and techniques for wafer-level optical testing by coupling probe light from top of the wafer.
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Roman R Malendevich from Sunnyvale, CA, age ~53 Get Report