Roger Brent Milne

6907584, Jun 14, 2005

Mar 14, 2003

10/388728

Roger B. Milne - Boulder CO, US
Jeffrey D. Stroomer - Lafayette CO, US

Xilinx, Inc. - San Jose CA

G06F017/50

716 1, 716 3

Method, apparatus, and computer readable medium for producing an interface description for an electronic design of an integrated circuit is described. By example, the electronic design includes a plurality of circuit descriptions representing the behavior of circuit elements. One or more circuit descriptions from the electronic design are selected to produce interface description. The one or more selected circuit descriptions include a subset of the plurality of circuit descriptions of the electronic design. A processor for modifying the electronic design is obtained. The electronic design is then processed using the processor with the interface description as parametric input.

6911840, Jun 28, 2005

Jun 6, 2003

10/456332

Roger B. Milne - Boulder CO, US
Jonathan B. Ballagh - Longmont CO, US

Xilinx, Inc. - San Jose CA

H03K007/38
H03K019/177

326 38, 326 37, 326 39, 326 41

An integrated circuit with overclocked embedded logic circuitry is described. In an example, a programmable logic device includes programmable logic blocks operable using a first clock signal having a first frequency. A dedicated logic circuit embedded within the programmable logic device is operable using a second clock signal synchronized with the first clock signal and having a second frequency, the second frequency being a multiple of the first frequency. An interface coupled between one or more of the programmable logic blocks and the dedicated logic circuit includes multiplexer circuitry to multiplex output signals produced by the one or more programmable logic blocks among input terminals of the dedicated logic circuit.

7003751, Feb 21, 2006

Jan 10, 2003

10/340498

Jeffrey D. Stroomer - Lafayette CO, US
Roger B. Milne - Boulder CO, US
Jonathan B. Ballagh - Longmont CO, US
Haibing Ma - Superior CO, US
L. James Hwang - Menlo Park CA, US
Nabeel Shirazi - San Jose CA, US

Xilinx Inc. - San Jose CA

G06F 17/50

716 11, 716 8, 345661

Method and apparatus for creating a circuit design. An object-oriented program instantiates a plurality of objects that model a circuit design. The objects have hierarchy attributes, connectivity attributes, and display attributes that describe a plurality of modules. The hierarchy attributes define parent-child relationships between modules, the connectivity attributes define input-output connections between modules, and the display attributes define a layout of the modules for viewing. Each of the objects has an associated method for generating a design specification in a selected format. When the program is executed, the design specification is generated from the set of objects. Depending on the capabilities of the available tools, the modules and logic elements are displayed in accordance with the display attributes either from the object-oriented program or from the design specification.

7007261, Feb 28, 2006

Mar 14, 2003

10/388711

Jonathan B. Ballagh - Longmont CO, US
Roger B. Milne - Boulder CO, US
Jeffrey D. Stroomer - Lafayette CO, US

Xilinx, Inc. - San Jose CA

G06F 17/50

716 17, 716 1, 716 2, 716 18

Method, apparatus, and computer readable medium for translating an electronic design of an integrated circuit into circuit description language is described. The electronic design includes a plurality of circuit descriptions representing behavior of circuit elements. A circuit description template is associated with a circuit description of the plurality of circuit descriptions. The circuit description template includes a first portion for fixed attributes of the circuit description and a second portion for variable attributes of the circuit description. One or more text processors are associated with the circuit description template. Variable attributes of the circuit description are related to the second portion of the circuit description template to produce a data structure. The circuit description template is processed using the one or more text processors with the data structure as parametric input.

7010664, Mar 7, 2006

Apr 30, 2003

10/427418

Jonathan B. Ballagh - Longmont CO, US
Eric R. Keller - Boulder CO, US
Roger B. Milne - Boulder CO, US

Xilinx, Inc. - San Jose CA

G06F 12/00

711218, 711100, 711154, 711200, 711217

A configurable address generator includes addressing sequence circuitry such as a set of counters. A set of comparators is also preferably included in the configurable address generator in order to detect different addressing conditions (e. g. , full, empty, etc. ). Coupled to these components is a plurality of programmable bits that allows the address generator to be configured to meet a number of different design requirements. For example, the configurable address generator can be configured as a stack pointer; it can also be configured to provide address generation for FIFO and MAC-based filter circuits, etc.

7068071, Jun 27, 2006

Oct 22, 2004

10/970962

Roger B. Milne - Boulder CO, US
Jonathan B. Ballagh - Longmont CO, US

Xilinx, Inc. - San Jose CA

H03K 7/38

326 41, 326 38, 326 47, 326 39

An integrated circuit with overclocked embedded logic circuitry is described. In an example, a programmable logic device includes programmable logic blocks operable using a first clock signal having a first frequency. A dedicated logic circuit embedded within the programmable logic device is operable using a second clock signal synchronized with the first clock signal and having a second frequency, the second frequency being a multiple of the first frequency. An interface coupled between one or more of the programmable logic blocks and the dedicated logic circuit includes multiplexer circuitry to multiplex output signals produced by the one or more programmable logic blocks among input terminals of the dedicated logic circuit.

7082594, Jul 25, 2006

Nov 18, 2003

10/717041

Roger B. Milne - Boulder CO, US
Jeffrey D. Stroomer - Lafayette CO, US

Xilinx, Inc. - San Jose CA

G06F 17/50

716 18, 716 1, 716 4

Methods and apparatus are disclosed for compiling high-level blocks of an electronic hardware design in a high-level modeling system (HLMS) into hardware description language (HDL) components. Clock requirements are established, along with (optionally) explicit connections from implicit connections between the high-level blocks. In one pass through the high-level blocks, HDL components are generated that are consistent with the clock requirements and explicit connections, if any.

7086030, Aug 1, 2006

Aug 4, 2003

10/633830

Jeffrey D. Stroomer - Lafayette CO, US
Roger B. Milne - Boulder CO, US
Haibing Ma - Superior CO, US
Jonathan B. Ballagh - Longmont CO, US

Xilinx, Inc. - San Jose CA

G06F 17/50

716 18, 716 3, 716 4

Method and apparatus for preparing a design in a high-level modeling system. Hardware description language (HDL) code is generated for one or more of a plurality of high-level subsystems in a high-level design tagged by the user for HDL code generation. Previously generated HDL code may be reused instead of generating new HDL code for each subsystem tagged by the user for HDL code reuse.