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Reinaldo A Bergamaschi

from Tarrytown, NY
Age ~64
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Also known as:
Reinald A Bergamaschi
Phone and address:
9 Windle Park, North Tarrytown, NY 10591
(914) 332-4815
Related to:
Karen Sue Tompkins, 60Gary E MossRosa Ross, 87Katherine M Rosswhite, 62Ronald J Ross, 93
Connected to:
Chad A Bergamaschi, 36Davide Bergamasco, 56Kimberly A Bergamasco, 52Rosa M Bergamasco, 56Sergio Bergamasco, 63Anne B Bergamesca, 64David F Bergamesca, 59Alyssa L Bergamini, 32Annette E Bergamini, 67Bianca N Bergamine, 42

Reinaldo Bergamaschi Phones & Addresses

  • 9 Windle Park, Tarrytown, NY 10591 (914) 332-4815
  • 9A Windle Park, Tarrytown, NY 10591 (914) 332-4815
  • North Tarrytown, NY
  • 9A Windle Park, Tarrytown, NY 10591 (914) 494-4863

Work

Company: Odysci Dec 2008 Position: Founder and ceo

Education

Degree: PhD School / High School: University of Southampton 1985 to 1989 Specialities: Electrical Eng. and Computer Science

Skills

Algorithms • Software Engineering • Software Development • C • Machine Learning • Embedded Systems • Simulations • Computer Science • C++ • System Architecture • Distributed Systems • Data Mining • Python • Linux • Programming • Agile Methodologies • Vhdl • Perl • High Performance Computing • Electronics • Signal Processing • High Performance Computing

Languages

Portuguese • English • Spanish

Awards

Ieee fellow • Acm distinguished scientist

Interests

Science and Technology • Education

Emails

j***[email protected]

Industries

Information Technology And Services

Resumes

Resumes

Reinaldo Bergamaschi Photo 1

Founder And Chief Executive Officer

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Location:
San Luis Obispo, CA
Industry:
Information Technology And Services
Work:
Odysci since Dec 2008
Founder and CEO
Institute of Computing, State University of Campinas (UNICAMP) Mar 2009 - Jun 2012
Visiting Professor
CadComponents Jun 2008 - Jun 2010
Founder and Chief Scientist
IBM T. J. Watson Research Center Apr 1989 - Dec 2007
Research Staff Member
Education:
University of Southampton 1985 - 1989
PhD, Electrical Eng. and Computer Science Philips International Institute, Eindhoven 1983 - 1984
MEE, Electronics Engineering Aeronautics Institute of Technology (ITA) 1979 - 1982
Bachelors, Electronics Engineering
Skills:
Algorithms
Software Engineering
Software Development
C
Machine Learning
Embedded Systems
Simulations
Computer Science
C++
System Architecture
Distributed Systems
Data Mining
Python
Linux
Programming
Agile Methodologies
Vhdl
Perl
High Performance Computing
Electronics
Signal Processing
High Performance Computing
Interests:
Science and Technology
Education
Languages:
Portuguese
English
Spanish
Awards:
IEEE Fellow
ACM Distinguished Scientist

Business Records

Name / Title
Company / Classification
Phones & Addresses
Reinaldo A Bergamaschi
CADCOMPONENTS, INC
1 Maiden Ln, New York, NY 10038
9A Windle Park, Tarrytown, NY 10591

Publications

Us Patents

Methods And Arrangements For Automatically Interconnecting Cores In Systems-On-Chip

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US Patent:
6993740, Jan 31, 2006
Filed:
Apr 3, 2000
Appl. No.:
09/542024
Inventors:
Reinaldo A. Bergamaschi - Tarrytown NY, US
Subhrajit Bhattacharya - White Plains NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716 12, 716 13, 716 14
Abstract:
A method and algorithms for creating correct-by-construction interconnections among complex intellectual property (IP) cores with hundreds of pins. The methods contemplated herein significantly reduce the time, complexity and potential for errors associated with systems-on-chip (SoC) integration.

Logic Block Timing Estimation Using Conesize

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US Patent:
7676779, Mar 9, 2010
Filed:
Sep 11, 2007
Appl. No.:
11/853235
Inventors:
Reinaldo A. Bergamaschi - Tarrytown NY, US
Sean M. Carey - Hyde Park NY, US
Brian W. Curran - Saugerties NY, US
Prabhakar N. Kudva - New York NY, US
Matthew E. Mariani - York Haven PA, US
Mark D. Mayo - Wappingers Falls NY, US
Ruchir Puri - Baldwin Place NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
G06F 9/45
US Classification:
716 6, 716 5, 716 18, 703 13, 703 14
Abstract:
A system for logic block timing analysis may include a controller, and storage in communication with the controller. The storage may provide delay-versus-conesize values of a logic block. The system may further include a fitting module to provide a delay-cone based upon the delay-versus-conesize values of the logic block. The system may also include a conesize parser that uses the delay-cone to provide delay values through the logic block. The conesize parser may be used to validate the design of the logic block by comparing the delay-cone with a desired cycle time.

Self-Tuning Power Management Techniques

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US Patent:
8001405, Aug 16, 2011
Filed:
Aug 29, 2008
Appl. No.:
12/201821
Inventors:
Gero Dittmann - New York NY, US
Reinaldo A. Bergamaschi - Tarrytown NY, US
Indira Nair - Briarcliff Manor NY, US
Alper Buyuktosunoglu - White Plains NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1/26
G06F 1/00
G06F 11/00
G01R 21/00
US Classification:
713320, 713300, 702 60, 714 10, 714 471
Abstract:
Power management techniques include a method for power management of a processor chip which comprises the following steps. An initial operating level is set for the processor chip. After a predetermined time interval, slack is calculated. If the slack is greater than zero, the initial operating level is increased to a next higher level, otherwise the initial operating level is maintained. After the predetermined time interval, the slack is re-calculated and further includes accumulated slack. If the re-calculated slack is greater than zero, the operating level is increased to the next higher level if the processor chip is being operated at the initial operating level, otherwise the operating level is returned to the initial operating level if the processor chip is being operated at the next higher operating level. The steps to re-calculate the slack and either increase the operating level to the next higher level or return the operating level to the initial operating level are repeated.

System To Identify Timing Differences From Logic Block Changes And Associated Methods

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US Patent:
20090070720, Mar 12, 2009
Filed:
Sep 11, 2007
Appl. No.:
11/853276
Inventors:
Reinaldo A. Bergamaschi - Tarrytown NY, US
Sean M. Carey - Hyde Park NY, US
Brian W. Curran - Saugerties NY, US
Prabhakar N. Kudva - New York NY, US
Lawrence Lange - Wappingers Falls NY, US
Matthew E. Mariani - York Haven PA, US
Mark D. Mayo - Wappingers Falls NY, US
Ruchir Puri - Baldwin Place NY, US
Gebhard Weber - Baden Wortemberg, DE
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:
G06F 17/50
US Classification:
716 6
Abstract:
A system to identify timing differences due to logic block changes, the system may include a controller, and storage in communication with the controller. The controller may provide delay values of a previous logic block and a current logic block. The system may also include a timing-modeler to compare the delay values of the previous logic block with the current logic block for timing analysis. The system may further include an interface that provides a report based upon the previous logic block and the current logic block comparison.

Optimal Performance And Power Management With Two Dependent Actuators

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US Patent:
20100057404, Mar 4, 2010
Filed:
Aug 29, 2008
Appl. No.:
12/201877
Inventors:
Gero Dittmann - New York NY, US
Alper Buyuktosunoglu - White Plains NY, US
Indira Nair - Briarcliff Manor NY, US
Reinaldo A. Bergamaschi - Tarrytown NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 19/00
G05B 13/02
US Classification:
702186, 700 28
Abstract:
Techniques for processor chip power management and performance optimization are provided. In one aspect, a method for maximizing performance of a processor chip within a given power consumption budget is provided. The method comprises the following steps. A power consumption and performance of the processor chip at all possible voltage level and frequency combinations is predicted. The processor chip is adjusted to the voltage level and frequency combination that provides the highest performance while having a power consumption that does not exceed the power budget. After a time interval t, the frequency of the processor chip is varied to accommodate for any shift in workload to maintain the highest performance within the power budget. After a time interval t, the adjust and vary steps are repeated, wherein time interval tis greater than time interval t.

Synthesis Of Arrays And Records

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US Patent:
63246805, Nov 27, 2001
Filed:
Aug 30, 1999
Appl. No.:
9/385307
Inventors:
Stephen Barnfield - New York NY
Reinaldo A. Bergamaschi - Tarrytown NY
Pradip K. Jha - Wappingers Falls NY
Rudra Mukherjee - Santa Clara CA
John D. Weaver - Milbrook NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1750
US Classification:
716 18
Abstract:
A method for synthesizing aggregate data types, in accordance with the present invention, includes representing aggregate data types in a control data flow graph, by representing aggregate objects as operand nodes, and operations on the aggregate objects as operation nodes. One-dimensional bit vectors are formed for the operand nodes, by recursively traversing through fields of the aggregate data type associated with the aggregate objects. Read and write operation nodes are formed in the control data flow graph for representing language constructs for accessing the aggregate objects. The control data flow graph is mapped onto hardware.
Control profile
Reinaldo A Bergamaschi from Tarrytown, NY, age ~64 Get Report