Ravindhar Kumar Kaw

6738583, May 18, 2004

May 1, 2000

09/561691

Farid Matta - Los Altos CA
Storrs T. Hoen - Brisbane CA
Ravindhar K. Kaw - Los Altos CA
Robert C. Taber - Palo Alto CA
Jason T. Hartlove - Saratoga CA

Agilent Technologies, Inc. - Palo Alto CA

H04B 1000

398131, 398129, 398156

An optical port with directional control. The port includes a transmitter, receiver, and first actuator. The transmitter generates an outgoing light signal that propagates in a transmission direction in response to an outgoing electrical signal. The receiver receives an incoming light signal and generating an incoming electrical signal therefrom, the receiver having a reception direction aligned with the transmission direction. The first actuator alters the transmission direction of the outgoing light signal in response to a first control signal. In one embodiment, the first actuator determines the direction of the outgoing light signal in a first plane, and a second actuator controls the direction of the outgoing light signal by an amount determined by a second control signal. The second actuator controls the direction of the outgoing light signal in a second plane that is orthogonal to the first plane. The actuators can be constructed from beam deflectors that utilize moveable mirrors to alter the transmission direction.

7202546, Apr 10, 2007

Oct 3, 2003

10/678980

Salvador Salcido, Jr. - Philomath OR, US
Michael G. Kelly - Corvallis OR, US
Michael D. Cusack - Boise ID, US
Ravindhar K. Kaw - San Jose CA, US

Avago Technologies General IP (Singapore) Pte. Ltd. - Singapore

H01L 29/00
H01L 23/58

257503, 257635, 257E21575

An integrated circuit including a copper interconnection layer includes an aluminum distribution layer overlying the copper interconnection layer to distribute external electrical signals such as power, ground, and clock signals throughout the die of the device. The distribution layer overlies the copper interconnection layer in a grid pattern which connects to the copper interconnection layer through a plurality of vias. The distribution layer further includes a plurality of wire bond pads to permit wire bonding between the distribution layer and bonding pads of the integrated circuit package.

7262508, Aug 28, 2007

Oct 3, 2003

10/678495

Michael G. Kelly - Corvallis OR, US
Ravindhar K. Kaw - San Jose CA, US

Avago Technologies General IP (Singapore) Pte. Ltd. - Singapore

H01L 23/48
H01L 23/52
H01L 29/40
H01L 23/02

257778, 257686, 257784, 257780, 257777, 257E23085

An integrated circuit incorporates flip chip and wire bonding techniques to provide an improved integrated circuit device. The integrated circuit device includes a package having a first plurality of bonding pads and a semiconductor substrate within the integrated circuit package and including a second plurality of bonding pads. A semiconductor substrate has a surface area. A plurality of wire bonds connect the first plurality of bonding pads to the second plurality of bonding pads. The device further includes an interconnection substrate mounted on the semiconductor substrate. The interconnection substrate has a surface area smaller than the semiconductor substrate surface area.

50218697, Jun 4, 1991

Dec 27, 1988

7/290496

Ravindhar K. Kaw - San Jose CA

Hewlett-Packard Company - Palo Alto CA

H01L 2312
H01L 2508
H01L 2512

357 75

An interconnection arrangement and technique for a single semiconductor chip containing incomplete electric circuitry and having electric surface terminations permitting said incomplete electric circuitry to be externally interconnected, the interconnection arrangement being mountable on the semiconductor chip and capable of electically communicating with the semiconductor chip through electric surface terminations on the top surface of the semiconductor chip and on the bottom surface of the interconnection arrangement.

50652800, Nov 12, 1991

Aug 30, 1990

7/575098

Marcos Karnezos - Menlo Park CA
Ravindhar Kaw - San Jose CA
Lawrence Hanlon - Menlo Park CA
Farid Matta - Mountain View CA

Hewlett-Packard Company - Palo Alto CA

H05K 720

361386

An electronic packaging module in which the inactive sides of integrated circuit chips are held in compression against a heat spreader by an elastomer pressed thereagainst by a multilayer flexible printed circuit board. A TAB frame, which may be demountable, interconnects integrated circuit chips to a multilayer flexible printed circuit board. A backing plate is fastened to a heat spreader so that it presses against the multilayer flexible printed circuit board. Contacts are compressed against the motherboard to interconnect the multilayer flexible printed circuit board thereto. Coaxial power connectors provide power and ground connections between non-peripheral portions of the multilayer flexible printed circuit board and the motherboard.