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Ranjeet K Pancholy

from Irvine, CA
Age ~75

Ranjeet Pancholy Phones & Addresses

  • 8 Sandpiper, Irvine, CA 92604
  • 115 El Camino Real, Menlo Park, CA 94025 (408) 621-1512
  • El Camino Real, Menlo Park, CA 94025
  • 1915 Water St, Milwaukee, WI 53202 (414) 225-9793
  • Mission Viejo, CA
  • Chicago, IL
  • Redlands, CA
  • San Diego, CA
  • Saratoga, CA
  • Cupertino, CA
  • Forest Park, IL

Resumes

Resumes

Ranjeet Pancholy Photo 1

Exec Director At Seagate Technology

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Position:
Exec Director at Seagate Technology
Location:
San Francisco Bay Area
Industry:
Computer Hardware
Work:
Seagate Technology
Exec Director
Ranjeet Pancholy Photo 2

Exec Director Vlsi Manufacturing At Seagate Technology

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Position:
Exec Director VLSI Manufacturing at Seagate Technology
Location:
San Francisco Bay Area
Industry:
Computer Hardware
Work:
Seagate Technology
Exec Director VLSI Manufacturing
Ranjeet Pancholy Photo 3

Ranjeet Pancholy

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Location:
United States

Business Records

Name / Title
Company / Classification
Phones & Addresses
Ranjeet Kumar Pancholy
Owner
Kesar Technology
Mfg Semiconductors/Related Devices
21215 Chadwick Ct, Saratoga, CA 95070
PO Box 1315, Cupertino, CA 95015
Ranjeet Pancholy
Sales And Marketing Executive
Nature Traditions
Misc Personal Services
115 El Camino Real, Menlo Park, CA 94025

Publications

Us Patents

Method For Reducing Surface Recombination Velocities In Iii-V Compound Semiconductors

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US Patent:
41706668, Oct 9, 1979
Filed:
May 11, 1977
Appl. No.:
5/796118
Inventors:
Ranjeet K. Pancholy - Mission Viejo CA
Gordon J. Kuhlmann - Newport Beach CA
D. Howard Phillips - Orange CA
Assignee:
Rockwell International Corporation - El Segundo CA
International Classification:
B05D 512
US Classification:
427 82
Abstract:
III-V compound semiconductors having native dielectrics thereon which are thermally grown from special composition surface layers thereof are provided with reduced surface recombination velocities by proper selection of the surface layer's composition and extent of conversion to the dielectric.

Gaas Crystal Surface Passivation Method

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US Patent:
43022782, Nov 24, 1981
Filed:
Jun 16, 1980
Appl. No.:
6/159465
Inventors:
Ranjeet K. Pancholy - Irvine CA
Rene Drouet - Placentia CA
Assignee:
Rockwell International Corporation - El Segundo CA
International Classification:
C30B 3300
H01L 21203
H01L 21316
US Classification:
156610
Abstract:
Reheating the cooled wafer product of the known method of forming thermal oxide surface passivation layers on GaAs crystal wafers, i. e. heating the wafer in contact with thermally vaporized As. sub. 2 O. sub. 3 in a substantially oxygen free closed vessel at a reaction temperature in excess of 450 degrees, from a temperature lower than the reaction temperature to a temperature higher than the reaction temperature and in the presence of free oxygen increases the compositional, physical and electrical uniformity of the surface layer.

Method For Passivating Iii-V Compound Semiconductors

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US Patent:
41729064, Oct 30, 1979
Filed:
May 11, 1977
Appl. No.:
5/796120
Inventors:
Ranjeet K. Pancholy - Mission Viejo CA
Assignee:
Rockwell International Corporation - El Segundo CA
International Classification:
B05D 512
US Classification:
427 82
Abstract:
High quality native surface passivation dielectrics on Group III-Group V compound semiconductors are produced by thermal conversion of a surface layer having a specially provided composition. The electrical properties of these dielectrics meet the requirements for dielectric and passivation layers over semiconductor devices generally and in field effect devices in particular.
Ranjeet K Pancholy from Irvine, CA, age ~75 Get Report