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Ranadeep O Dutta

from Del Mar, CA
Age ~61
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Also known as:
Ranadeep Butta, Dutta O Ranadeep
Phone and address:
2742 Caminito San Pablo APT 27, Del Mar, CA 92014
Related to:
Carmelo L Rivera, 79Luis A Rivera, 64Violetta Rivera, 67Kayla Rivera, 36Alejandro O Rivera, 90Janice Rivera, 54
Connected to:
Alok Dutta, 70Apurba R Dutta, 69Aradhana Dutta, 46Biswanath Dutta, 34Chandana Dutta, 47Debaditya Dutta, 40Debanjana Dutta, 39Debjani Dutta, 54Debojyoti Dutta, 35Dipen D Dutta, 77

Ranadeep Dutta Phones & Addresses

  • 2742 Caminito San Pablo APT 27, Del Mar, CA 92014
  • 9323 Lightwood Cv, Austin, TX 78748 (512) 280-1728
  • San Diego, CA
  • Campbell, CA
  • El Segundo, CA
  • Redondo Beach, CA
  • 9323 Lightwood Loop, Austin, TX 78748 (512) 750-4566

Work

Position: Production Occupations

Education

Degree: Associate degree or higher

Resumes

Resumes

Ranadeep Dutta Photo 1

Ranadeep Dutta

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Location:
United States

Publications

Us Patents

Bipolar Transistor With Geometry Optimized For Device Performance, And Method Of Making Same

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US Patent:
7253498, Aug 7, 2007
Filed:
Jul 6, 2004
Appl. No.:
10/885250
Inventors:
Ranadeep Dutta - Austin TX, US
Assignee:
Legerity Inc. - Austin TX
International Classification:
H01L 27/82
US Classification:
257571, 257566, 257578, 257583, 257591, 257592
Abstract:
The present invention is generally directed to bipolar transistors with geometry optimized for device performance and various methods of making same. In one illustrative embodiment, the device includes a substrate, an intrinsic base region formed in the substrate, a continuous emitter region formed within the intrinsic base region, the emitter region having a plurality of substantially hexagonal shaped openings defined therein, and a plurality of extrinsic base regions formed in the substrate, wherein each of the extrinsic base regions is positioned within an area defined by one of the plurality of substantially hexagonal shaped openings.

Methods Of Forming A P-Well In An Integrated Circuit Device

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US Patent:
7273776, Sep 25, 2007
Filed:
Jul 27, 2004
Appl. No.:
10/899596
Inventors:
Ranadeep Dutta - Austin TX, US
Frank L. Thiel - Austin TX, US
Assignee:
Legerity, Inc. - Austin TX
International Classification:
H01L 21/8238
US Classification:
438224, 438228, 257E2163, 257E21644
Abstract:
The present invention is generally directed to a method of forming a p-well in an integrated circuit device. In one illustrative embodiment, the method comprises forming a first layer of epitaxial material above an active layer of a substrate, forming a first doped region in the first layer of epitaxial material, forming a second layer of epitaxial material above the first layer of epitaxial material, forming a second doped region in the second layer of epitaxial material, and performing at least one heat treating process.

High Voltage Mosfet Devices Containing Tip Compensation Implant

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US Patent:
20090170269, Jul 2, 2009
Filed:
Dec 31, 2007
Appl. No.:
11/968135
Inventors:
Ranadeep Dutta - Campbell CA, US
International Classification:
H01L 21/336
US Classification:
438289, 257E21409
Abstract:
Semiconductor devices and methods for making semiconductor devices are described in this application. The semiconductor devices comprise a MOSFET device in a semiconductor substrate, with the MOSFET device containing source and drain regions with a tip implant region near the surface of the substrate. The tip implant region contains a tip compensation implant region located under the gate of the MOSFET device that overlaps with the source and drain. The tip compensation implant region reduces the dopant concentration in this gate-drain overlap region, while maintaining a graded drain-well junction profile, thereby reducing the band to band tunneling and increasing the drain breakdown voltage. Other embodiments are described.

3D Inductor Design Using Bundle Substrate Vias

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US Patent:
20220406882, Dec 22, 2022
Filed:
Jun 16, 2021
Appl. No.:
17/349724
Inventors:
- San Diego CA, US
Je-Hsiung LAN - San Diego CA, US
Ranadeep DUTTA - Del Mar CA, US
International Classification:
H01L 49/02
H01L 23/48
H01L 21/768
H01L 23/66
H01P 3/08
H01P 11/00
Abstract:
A three dimensional (3D) inductor is described. The 3D inductor includes a first plurality of micro-through substrate vias (TSVs) within a first area of a substrate. The 3D inductor also includes a first trace on a first surface of the substrate, coupled to a first end of the first plurality of micro-TSVs. The 3D inductor further includes a second trace on a second surface of the substrate, opposite the first surface, coupled to a second end, opposite the first end, of the first plurality of micro-TSVs.

Stacked Inductor Having A Discrete Metal-Stack Pattern

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US Patent:
20220285080, Sep 8, 2022
Filed:
Mar 8, 2021
Appl. No.:
17/195220
Inventors:
- San Diego CA, US
Changhan Hobie YUN - San Diego CA, US
Je-Hsiung LAN - San Diego CA, US
Ranadeep DUTTA - Del Mar CA, US
International Classification:
H01F 27/28
H04B 1/40
H04B 1/18
H03H 7/01
H01L 49/02
H01F 41/04
Abstract:
An inductor includes a first metallization layer multi-turn trace. The inductor also includes a second metallization layer multi-turn trace coupled to the first metallization layer multi-turn trace through at least one first via. The inductor further includes a plurality of discrete third metallization layer trace segments coupled to the second metallization layer multi-turn trace through a plurality of second vias.

Three-Dimensional (3D) Integrated Circuit With Passive Elements Formed By Hybrid Bonding

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US Patent:
20210398957, Dec 23, 2021
Filed:
Jun 19, 2020
Appl. No.:
16/906509
Inventors:
- San Diego CA, US
Ranadeep DUTTA - Del Mar CA, US
Jonghae KIM - San Diego CA, US
International Classification:
H01L 25/16
H01L 23/00
H01L 49/02
H01L 27/092
H03H 9/17
Abstract:
A three-dimensional integrated circuit (3DIC) and techniques for fabricating a 3DIC. An example semiconductor device generally includes an integrated circuit (IC) having a first plurality of pads coupled to components of the IC, wherein a first oxide material is disposed between the first plurality of pads, and a second plurality of pads, wherein at least a portion of the first plurality of pads is bonded to at least a portion of the second plurality of pads, and wherein a second oxide material is disposed between the second plurality of pads and is bonded to the first oxide material b. The semiconductor device may also include a substrate disposed above the second plurality of pads, one or more passive devices adjacent to the substrate, and one or more vias formed through the substrate, wherein at least one of the second plurality of pads is coupled to the one or more vias.

Advanced Integrated Passive Device (Ipd) With Thin-Film Heat Spreader (Tf-Hs) Layer For High Power Handling Filters In Transmit (Tx) Path

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US Patent:
20210391234, Dec 16, 2021
Filed:
Jun 10, 2020
Appl. No.:
16/898096
Inventors:
- San Diego CA, US
Jonghae KIM - San Diego CA, US
Ranadeep DUTTA - Del Mar CA, US
International Classification:
H01L 23/367
H01L 23/373
H01L 21/48
Abstract:
A semiconductor package is described. The semiconductor package includes a passive substrate and a first integrated passive device (IPD) in a first interlayer-dielectric (ILD) layer on the passive substrate. The semiconductor package also includes a second ILD layer on the first ILD layer. The semiconductor package further includes a second IPD in a third ILD layer on the second ILD layer. The semiconductor package also includes a thermal mitigation structure on inductive elements of the second IPD.

Package Comprising Stacked Filters With A Shared Substrate Cap

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US Patent:
20210376810, Dec 2, 2021
Filed:
May 27, 2020
Appl. No.:
16/884891
Inventors:
- San Diego CA, US
Je-Hsiung LAN - San Diego CA, US
Ranadeep DUTTA - Del Mar CA, US
Milind SHAH - San Diego CA, US
Periannan CHIDAMBARAM - San Diego CA, US
International Classification:
H03H 9/05
H01L 41/053
H01L 41/047
H03H 9/145
H01L 25/04
H03H 9/64
H01L 41/23
H03H 3/02
H03H 9/02
Abstract:
A package that includes a first filter comprising a first polymer, a substrate cap, a second filter comprising a second polymer frame, at least one interconnect, an encapsulation layer and a plurality of through encapsulation vias. The substrate cap is coupled to the first polymer frame such that a first void is formed between the substrate cap and the first filter. The second polymer frame is coupled to the substrate cap such that a second void is formed between the substrate cap and the second filter. The at least one interconnect is coupled to the first filter and the second filter. The encapsulation layer encapsulates the first filter, the substrate cap, the second filter, and the at least one interconnect. The plurality of through encapsulation vias coupled to the first filter.
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Ranadeep O Dutta from Del Mar, CA, age ~61 Get Report