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Ramesh Chandra Tekumalla

from Breinigsville, PA
Age ~54
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Also known as:
Ramesh C Tekumalla, Ramesh Cha Tekumalla, Ramesh Cha Murty, Ramesh Chandra Murty, Remesh Tekumalla, Tekumalla Ramesh Cha, Tekumalla Rames, Tekumalla Rc
Phone and address:
8670 Lockwood Rd, Breinigsville, PA 18031
Related to:
Susan M Cha, 43
Connected to:
Karen A Tekverk, 58Amit N Tekwani, 42Florence K Tela, 54Yacob Telahun, 40Leilani E Telan, 78Suzanne M Telan, 51Juliette L Telander, 66Aniket S Telang, 38Dattaraj Telang, 39Prajakta Telang, 40

Ramesh Tekumalla Phones & Addresses

  • 8670 Lockwood Rd, Breinigsville, PA 18031
  • 34 Summer Hill Rd, Dracut, MA 01826 (978) 689-1893
  • 500 Broadway, Malden, MA 02148 (781) 324-4079
  • 980 163Rd Ave, Beaverton, OR 97006 (503) 617-9278
  • Amherst, MA

Work

Company: Amd Position: Staff engineer

Education

School / High School: University of Massachusetts, Amherst 1994 to 1997

Industries

Computer Hardware

Resumes

Resumes

Ramesh Tekumalla Photo 1

Staff Engineer At Amd

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Position:
Staff Engineer at AMD
Location:
Greater Boston Area
Industry:
Computer Hardware
Work:
AMD
Staff Engineer
Education:
University of Massachusetts, Amherst 1994 - 1997

Publications

Us Patents

Reducing Verification Time For Integrated Circuit Design Including Scan Circuits

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US Patent:
6886145, Apr 26, 2005
Filed:
Jul 22, 2002
Appl. No.:
10/201711
Inventors:
Scott Davidson - Fremont CA, US
Ramesh C. Tekumalla - Malden MA, US
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
G06F017/50
US Classification:
716 6, 716 4, 716 7, 716 12
Abstract:
A testbench for an integrated circuit (IC) design including a chain of scan circuits having a memory characteristic is verified by: (a) dividing the chain of scan circuits and creating a plurality of partitions, each partition including at least one logic cone output, each scan circuit belonging to one of the partition as a logic cone output; (b) generating a partitioned netlist for each partition from a full netlist for the IC design, the partitioned netlist including at least one logic cone, the logic cone extending from the logic cone output to at least one logic cone input; (c) generating a partitioned testbench for each partition from the full testbench based on the partitioned netlists; and (d) performing verification for the testbench by simulating the partitioned testbenches on the corresponding partitioned netlists.

Low-Power And Area-Efficient Scan Cell For Integrated Circuit Testing

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US Patent:
8566658, Oct 22, 2013
Filed:
Aug 24, 2011
Appl. No.:
13/216336
Inventors:
Ramesh C. Tekumalla - Breinigsville PA, US
Priyesh Kumar - Pune, IN
Prakash Krishnamoorthy - Bethlehem PA, US
Parag Madhani - Allentown PA, US
Assignee:
LSI Corporation - San Jose CA
International Classification:
G01R 31/28
US Classification:
714729, 714727
Abstract:
An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells, with the scan chain being configured to operate as a serial shift register in a scan shift mode of operation and to capture functional data from at least a portion of the additional circuitry in a functional mode of operation. At least a given one of the scan cells of the scan chain comprises output control circuitry which is configured to disable a functional data output of the scan cell in the scan shift mode of operation and to disable a scan output of the scan cell in the functional mode of operation.

Scan Test Circuitry Comprising Scan Cells With Multiple Scan Inputs

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US Patent:
8615693, Dec 24, 2013
Filed:
Aug 31, 2011
Appl. No.:
13/222663
Inventors:
Ramesh C. Tekumalla - Breinigsville PA, US
Assignee:
LSI Corporation - San Jose CA
International Classification:
G01R 31/28
US Classification:
714726, 714724, 714758
Abstract:
An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises scan cells configured to form scan chains. At least a given one of the scan cells is a multiple scan input scan cell having at least first and second scan inputs. In a first scan shift mode of operation, the given scan cell is configured with a first plurality of other scan cells into a scan chain of a first type using the first scan input. In a second scan shift mode of operation, the given scan cell is configured with a second plurality of other scan cells different than the first plurality of other scan cells into a scan chain of a second type using the second scan input.

Scan Test Circuitry With Delay Defect Bypass Functionality

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US Patent:
8645778, Feb 4, 2014
Filed:
Dec 31, 2011
Appl. No.:
13/341998
Inventors:
Ramesh C. Tekumalla - Breinigsville PA, US
Prakash Krishnamoorthy - Bethlehem PA, US
Assignee:
LSI Corporation - San Jose CA
International Classification:
G01R 31/28
US Classification:
714726
Abstract:
An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having scan cells. The scan test circuitry further comprises scan delay defect bypass circuitry comprising multiplexers arranged within the scan chain. At least a given one of the multiplexers is configured to allow a corresponding one of the scan cells to be selectively bypassed in a scan shift configuration of the scan cells responsive to a delay defect associated with that scan cell. A delay defect bypass controller may be used to generate a bypass control signal for controlling the multiplexer between at least a first state in which the corresponding scan cell is not bypassed and a second state in which the corresponding scan cell is bypassed.

Algorithms For Determining Path Coverages And Activity

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US Patent:
20030229488, Dec 11, 2003
Filed:
Jun 10, 2002
Appl. No.:
10/166904
Inventors:
Ramesh Tekumalla - Malden MA, US
Scott Davidson - Fremont CA, US
Assignee:
Sun Microsystems, Inc. - Palo Alto CA
International Classification:
G06F017/28
G06F017/50
US Classification:
704/004000
Abstract:
An apparatus and method are provided for identifying functionally sensitized data paths in a logic circuit and storing the identified data paths in a representation of the logic circuit. The representation of the logic circuit includes a single occurrence of each identified data path along with a variable for each single name or path segment identified. The variable represents a number of times that path segment or signal name was functionally sensitized.

Integrated Circuit Comprising Scan Test Circuitry With Parallel Reordered Scan Chains

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US Patent:
20120324303, Dec 20, 2012
Filed:
Jun 20, 2011
Appl. No.:
13/164345
Inventors:
Ramesh C. Tekumalla - Breinigsville PA, US
Prakash Krishnamoorthy - Bethlehem PA, US
Parag Madhani - Allentown PA, US
International Classification:
G01R 31/3177
G06F 11/25
US Classification:
714729, 714E11155
Abstract:
An integrated circuit comprises scan test circuitry and additional internal circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a plurality of scan chains, with each such scan chain comprising a plurality of flip-flops configurable to operate as a serial shift register. The plurality of scan chains are arranged in sets of two or more parallel scan chains. The scan test circuitry further comprises multiplexing circuitry, including a plurality of multiplexers each associated with a corresponding one of the sets of parallel scan chains and configured to multiplex scan test outputs from the parallel scan chains within the corresponding one of the sets of parallel scan chains. In one embodiment, one or more of the sets of parallel scan chains comprise respective pairs of parallel scan chains with each such pair corresponding to a single original scan chain. A given one of the pairs of parallel scan chains comprises an even scan chain and an odd scan chain, formed by reordering the corresponding single original scan chain.

Integrated Circuit Comprising Scan Test Circuitry With Controllable Number Of Capture Pulses

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US Patent:
20120331362, Dec 27, 2012
Filed:
Jun 21, 2011
Appl. No.:
13/165284
Inventors:
Ramesh C. Tekumalla - Breinigsville PA, US
International Classification:
G01R 31/3177
G06F 11/25
US Classification:
714731, 714E11155
Abstract:
An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a plurality of scan chains coupled to the additional circuitry, a scan capture clock generator configured to generate a scan capture clock signal having a controllable number of capture pulses, and a clock selection circuit configured to select between at least the scan capture clock signal and a scan shift clock signal for application to clock signal inputs of the scan chains. In one embodiment, the scan capture clock generator comprises a finite state machine, a plurality of capture clock pulse circuits each generating a capture clock pulse signal comprising a different number of capture clock pulses, and logic circuitry coupled to the finite state machine and having inputs adapted to receive the outputs of the capture clock pulse circuits. The logic circuitry is configured to provide at an output thereof at least a portion of a particular one of the capture clock pulse signals based on a current state of the finite state machine.

Efficient Wrapper Cell Design For Scan Testing Of Integrated Circuits

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US Patent:
20130007547, Jan 3, 2013
Filed:
Jun 30, 2011
Appl. No.:
13/173144
Inventors:
Ramesh C. Tekumalla - Breinigsville PA, US
Partho Tapan Chaudhuri - Pune, IN
Priyesh Kumar - Pune, IN
Komal N. Shah - Mumbai, IN
International Classification:
G01R 31/3177
G06F 11/25
US Classification:
714726, 714E11155
Abstract:
An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a plurality of scan chains, including at least one wrapper cell scan chain arranged between first and second circuitry cores of the additional circuitry, with the wrapper cell scan chain comprising a plurality of wrapper cells and being configurable to operate as a serial shift register in a scan shift mode of operation. At least one of the wrapper cells of the wrapper cell scan chain comprises a flip-flop having a throughput data path that is part of a scan shift path of the wrapper cell scan chain and not part of a functional path between the first and second circuitry cores. In an HDD controller embodiment, the first and second circuitry cores may comprise respective read channel and additional cores of a system-on-chip.
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Ramesh Chandra Tekumalla from Breinigsville, PA, age ~54 Get Report