US Patent:
20120175733, Jul 12, 2012
Inventors:
BERND E. KASTENMEIER - Austin TX, US
Raman E. Evazians - Pflugerville TX, US
International Classification:
H01L 27/08
H01L 21/02
US Classification:
257532, 438381, 438386, 257E21008, 257E27048
Abstract:
A device structure includes an inter-level dielectric, a via, a first conductive trench, and a second conductive trench. The inter-level dielectric has a top surface and a bottom surface. The via extends from the top surface to the bottom surface. The first conductive trench extends from the top surface to a first depth below the top surface. The second conductive trench extends from the top surface to a second depth below the top surface, wherein the second depth is above the bottom surface and below the first depth.