Rajan D Deshmukh

6441473, Aug 27, 2002

Jun 30, 2000

09/609582

Rajan D. Deshmukh - Pennington NJ

Agere Systems Guardian Corp. - Orlando FL

H01L 23495

257669, 257692, 257738, 257773, 257780, 257782, 22818022

An improved flip chip assembly is disclosed of the type where a semiconductor chip having a certain thermal expansion coefficient is directly mounted via solder bumps on the metallization pattern of a circuit substrate having a different thermal expansion coefficient. A base layer comprised of a polymer material is disposed over the surface of the chip, between the chip and the substrate, and the solder bumps are placed over the base layer; the base layer modifies the effective thermal expansion coefficient of the solder bumps to approximate that of the substrate, thus reducing the thermal expansion coefficient differential at the junction of the chip and the substrate.

6753118, Jun 22, 2004

Mar 27, 2002

10/109411

Rajan D. Deshmukh - Pennington NJ
Benjamin J. Eggleton - Summit NJ
Pavel Ivanoff Reyes - Murray Hill NJ
Carl Soccolich - Flemington NJ
Michael Sumetsky - Bridgewater NJ
Paul S. Westbrook - Chatham NJ

Fitel USA Corp. - Norcross GA

G03F 720

430 30, 290321, 359569, 385 37

A grating fabrication process utilizes real-time measurement of a grating characteristic (such as, for example, grating period chirp, reflectivity, group delay) as a feedback error signal to modify the writing process and improve the characteristics of the finished grating. A test beam is launched through the optical medium during the writing process (or at the end of an initial writing process) and a particular characteristic is measured and used to generate a âcorrectiveâ apodization refractive index profile that can be incorporated with the grating to improve its characteristics. The improvements may be applied to a phase (or amplitude) mask used to write the grating (etching, local deformation, coating changes, for example), or the grating itself may be corrected using additional UV exposure, non-uniform annealing, non-uniform heating, and/or non-uniform tensionâthese techniques applied separately or in an intermittent sequence. The utilization of a âclosed loopâ grating fabrication process provides the ability to form gratings with finely tuned characteristics.

6778734, Aug 17, 2004

Jan 15, 2002

10/047339

Kirk William Baldwin - Springfield NJ
Benjamin John Eggleton - Summit NJ
Kenneth Stephen Feder - Murray Hill NJ
Robert A. Macharrie - Easton PA
John A. Rogers - New Providence NJ
Paul Steinvurzel - Jersey City NJ
Jon Engelberth - Denville NJ
Rajan Deshmukh - Trenton NJ

Lucent Technologies Inc. - Murray Hill NJ

G02B 634

385 37

A thermally tunable optical fiber device comprises a length of optical fiber including a device disposed within a microcapillary heater. The microcapillary heater can include a thin film resistive heater. The fiber itself can optionally include a thin film resistive heater overlying the device, and a plurality of nested microcapillary tubes can optionally provide a plurality of successive concentric heaters overlying the device. The heaters films can be films with uniform, tapered or periodically varying thickness. The heaters can be single layer or multiple layer. Multiple layer films can be superimposed with intervening insulating layers or plural layers can be formed on different angular regions of the microcapillary. Thus one can provide virtually any desired temperature versus length profile along the fiber device.

6830999, Dec 14, 2004

Jun 17, 2002

10/173182

Rajan D. Deshmukh - Pennington NJ

Agere Systems Inc. - Allentown PA

H01L 2144

438612, 438613, 438622, 438623

An improved flip chip assembly is disclosed of the type where a semiconductor chip having a certain thermal expansion coefficient is directly mounted via solder bumps on the metallization pattern of a circuit substrate having a different thermal expansion coefficient. A base layer comprised of a polymer material is disposed over the surface of the chip, between the chip and the substrate, and the solder bumps are placed over the base layer; the base layer modifies the effective thermal expansion coefficient of the solder bumps to approximate that of the substrate, thus reducing the thermal expansion coefficient differential at the junction of the chip and the substrate.

52497330, Oct 5, 1993

Jul 16, 1992

7/915492

Michael F. Brady - Morrisville PA
Rajan D. Deshmukh - Yardley PA

AT&T Bell Laboratories - Murray Hill NJ

B23K 100
B23K 3538

22818022

A solder self-alignment process for aligning a semiconductor chip (13) with, and bonding the chip to, a substrate (12) is preformed in an atmosphere rich in gaseous formic acid, at least during the melting step. It is preferred that the formic acid atmosphere be maintained during the self-alignment step and the step of cooling and hardening the solder elements (23). With this feature, one can completely avoid the use of any solid or liquid fluxes and avoid the consequences of such use. Nonetheless, the molten solder elements (23) dependably bond to the bonding surfaces and vertically align themselves.

56729138, Sep 30, 1997

Jun 13, 1996

8/663336

Daniel Flanagan Baldwin - Monmouth Junction NJ
Rajan D. Deshmukh - Trenton NJ

Lucent Technologies Inc. - Murray Hill NJ

H01L 2348
H01L 2352
H01L 2940

257737

A semiconductor chip (10) has a plurality of metallized members (12) that are each advantageously bumped with a volume of gallium amalgam (18) to render the members wettable by a conventional solder.