Resumes
Resumes
Design Automation Engineer
View pageLocation:
Phoenix, AZ
Industry:
Semiconductors
Work:
Intel Corporation
Design Automation Engineer
Intel Corporation Oct 2015 - Nov 2016
Rtl2Gds Implementation Methodology Engineer
Intel Corporation Jun 1, 2014 - Oct 2015
Graphics Hardware Engineer
Intel Corporation Jun 2013 - May 2014
Gfx Design Intern
Embitech Solutions Dec 2011 - May 2012
Engineering Trainee
Design Automation Engineer
Intel Corporation Oct 2015 - Nov 2016
Rtl2Gds Implementation Methodology Engineer
Intel Corporation Jun 1, 2014 - Oct 2015
Graphics Hardware Engineer
Intel Corporation Jun 2013 - May 2014
Gfx Design Intern
Embitech Solutions Dec 2011 - May 2012
Engineering Trainee
Education:
Arizona State University 2012 - 2014
Masters, Computer Engineering L.d. College of Engineering 2008 - 2012
Bachelor of Engineering, Bachelors, Communication, Engineering, Electronics
Masters, Computer Engineering L.d. College of Engineering 2008 - 2012
Bachelor of Engineering, Bachelors, Communication, Engineering, Electronics
Skills:
Windows
Microsoft Office
Customer Service
C
C++
English
Negotiation
Linux Ubuntu
Proteus
Mplab
Matlab
Xilinx
Visual Basic
X86 Assembly
Mips
Cadence Virtuoso
Cadence Spectre
Cadence Virtuoso Layout Editor
Cadence Virtuoso Schematic Editor
Vlsi
Microcontrollers
Simulations
Verilog
Ubuntu
Circuit Design
Vhdl
Microsoft Office
Customer Service
C
C++
English
Negotiation
Linux Ubuntu
Proteus
Mplab
Matlab
Xilinx
Visual Basic
X86 Assembly
Mips
Cadence Virtuoso
Cadence Spectre
Cadence Virtuoso Layout Editor
Cadence Virtuoso Schematic Editor
Vlsi
Microcontrollers
Simulations
Verilog
Ubuntu
Circuit Design
Vhdl
Interests:
Social Services
Children
Outdoor Sports Tennis
Politics
Education
Microprocessor Architecture
Poverty Alleviation
Science and Technology
Cricket Football
Disaster and Humanitarian Relief
Digital Circuits Design
Swimming
Children
Outdoor Sports Tennis
Politics
Education
Microprocessor Architecture
Poverty Alleviation
Science and Technology
Cricket Football
Disaster and Humanitarian Relief
Digital Circuits Design
Swimming
Languages:
English
Hindi
Gujarati
French
Hindi
Gujarati
French
Raj Bhansali
View pageSkills:
Spotlight
Design Automation Engineer
View pageLocation:
Austin, TX
Work:
Design Automation Engineer
Raj Bhansali
View pageRaj Bhansali
View pageRaj Bhansali
View pageRaj Bhansali
View pageRaj Bhansali Tempe, AZ
View pageWork:
INTEL CORPORATION
Jun 2013 to 2000
GFX Design Intern
PC Selector
May 2014 to Present
32-bit NON PIPELINED SINGLE CYCLE MIPS PROCESSOR
Verilog
Mar 2013 to May 2013
8-BIT EVEN PARITY GENERATOR
Nov 2012 to Dec 2012
Cadence Virtuoso Schematic Editor
Embitech Solutions
Mar 2012 to May 2012
Trainee Engineer
Jun 2013 to 2000
GFX Design Intern
PC Selector
May 2014 to Present
32-bit NON PIPELINED SINGLE CYCLE MIPS PROCESSOR
Verilog
Mar 2013 to May 2013
8-BIT EVEN PARITY GENERATOR
Nov 2012 to Dec 2012
Cadence Virtuoso Schematic Editor
Embitech Solutions
Mar 2012 to May 2012
Trainee Engineer
Education:
Arizona State University
Tempe, AZ
May 2014
M.S in Computer Engineering
L.D. College of Engineering
Ahmedabad, Gujarat
Aug 2008 to May 2012
B.E in Electronics and Communication Engineering
Tempe, AZ
May 2014
M.S in Computer Engineering
L.D. College of Engineering
Ahmedabad, Gujarat
Aug 2008 to May 2012
B.E in Electronics and Communication Engineering