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Raghu P Chalasani

from San Jose, CA
Age ~64
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Also known as:
Raghu Chalafani
Phone and address:
250 Brandon St APT 320, San Jose, CA 95134
Related to:
Ufha ChalasaniUsha Chalasani, 58
Connected to:
Beatriz A Chalas, 43Cristian Chalas, 39Edward J Chalas, 40Jagadish Chalasani, 51John Chalas, 31Lalitha Chalasani, 60Narayan Chalasani, 41Phani P Chalasani, 37Rama P Chalasani, 65Sahithi Chalasani, 37

Raghu Chalasani Phones & Addresses

  • 250 Brandon St APT 320, San Jose, CA 95134
  • 305 Elan Village Ln, San Jose, CA 95134

Publications

Us Patents

Method And System For Distributing Clock Signals On Non-Manhattan Semiconductor Integrated Circuits

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US Patent:
7644384, Jan 5, 2010
Filed:
Aug 14, 2006
Appl. No.:
11/464478
Inventors:
Steven Teig - Menlo Park CA, US
Raghu Chalasani - San Jose CA, US
Akira Fujimura - Saratoga CA, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 12, 716 11, 716 18
Abstract:
The present invention introduces methods, systems, and architectures for routing clock signals in an integrated circuit layout. The introduced clock signal clock signal structures are rendered with non Manhattan routing. In a first embodiment, the traditional recursive H clock signal structure is rendered after transforming the coordinates system such that a rotated recursive H clock signal structure is rendered. In another embodiment, a recursive Y structure is used to create a clock signal structure. The recursive Y structure may also be implemented in a rotated alignment. For clock signal redundancy, non Manhattan wiring may be used to create a clock signal mesh network.

Method And System For Distributing Clock Signals On Non Manhattan Semiconductor Integrated Circuit Using Parameterized Rotation

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US Patent:
7730441, Jun 1, 2010
Filed:
Oct 11, 2006
Appl. No.:
11/548655
Inventors:
Steven Teig - Menlo Park CA, US
Raghu Chalasani - San Jose CA, US
Akira Fujimura - Saratoga CA, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 12, 716 1, 716 9, 716 11
Abstract:
The present invention introduces methods, systems, and architectures for routing clock signals in an integrated circuit layout. The introduced clock signal clock signal structures are rendered with non Manhattan routing. In a first embodiment, the traditional recursive H clock signal structure is rendered after transforming the coordinates system such that a rotated recursive H clock signal structure is rendered. In another embodiment, a recursive Y structure is used to create a clock signal structure. The recursive Y structure may also be implemented in a rotated alignment. For clock signal redundancy, non Manhattan wiring may be used to create a clock signal mesh network.

Method And System For Distributing Clock Signals On Non Manhattan Semiconductor Integrated Circuits

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US Patent:
8438525, May 7, 2013
Filed:
Dec 21, 2009
Appl. No.:
12/644001
Inventors:
Steven Teig - Menlo Park CA, US
Raghu Chalasani - San Jose CA, US
Akira Fujimura - Saratoga CA, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716126, 716113, 716119, 716139
Abstract:
The present invention introduces methods, systems, and architectures for routing clock signals in an integrated circuit layout. The introduced clock signal clock signal structures are rendered with non Manhattan routing. In a first embodiment, the traditional recursive H clock signal structure is rendered after transforming the coordinates system such that a rotated recursive H clock signal structure is rendered. In another embodiment, a recursive Y structure is used to create a clock signal structure. The recursive Y structure may also be implemented in a rotated alignment. For clock signal redundancy, non Manhattan wiring may be used to create a clock signal mesh network.

Tolerable Flare Difference Determination

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US Patent:
8533636, Sep 10, 2013
Filed:
Oct 21, 2011
Appl. No.:
13/279176
Inventors:
Sergiy Komirenko - Cupertino CA, US
Nicolas Bailey Cobb - Sunnyvale CA, US
Raghu Chalasani - San Jose CA, US
Assignee:
Mentor Graphics Corporation - Wilsonville OR
International Classification:
G06F 17/50
US Classification:
716 51, 716 53
Abstract:
Aspects of the invention relate to techniques for compensating flare effects in a lithographic process for an array of identical circuits to be fabricated on a wafer. According to various implementations of the invention, a reference circuit is selected from the array of identical circuits and intolerable flare difference regions are determined based on flare difference layers and tolerable flare difference layers. The lithographic process result for the array of identical circuit may be derived from that for the reference circuit and the intolerable flare difference regions.

Method And System For Distributing Clock Signals On Non Manhattan Semiconductor Integrated Circuits

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US Patent:
20100213982, Aug 26, 2010
Filed:
May 3, 2010
Appl. No.:
12/772967
Inventors:
Steven Teig - Menlo Park CA, US
Raghu Chalasani - San Jose CA, US
Akira Fujimura - Saratoga CA, US
International Classification:
H03K 19/00
G06F 17/50
US Classification:
326 93, 716 12
Abstract:
The present invention introduces methods, systems, and architectures for routing clock signals in an integrated circuit layout. The introduced clock signal clock signal structures are rendered with non Manhattan routing. In a first embodiment, the traditional recursive H clock signal structure is rendered after transforming the coordinates system such that a rotated recursive H clock signal structure is rendered. In another embodiment, a recursive Y structure is used to create a clock signal structure. The recursive Y structure may also be implemented in a rotated alignment. For clock signal redundancy, non Manhattan wiring may be used to create a clock signal mesh network.

Method And System For Distributing Clock Signals On Non Manhattan Semiconductor Integrated Circuits

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US Patent:
7117470, Oct 3, 2006
Filed:
Oct 10, 2003
Appl. No.:
10/684211
Inventors:
Steven Teig - Menlo Park CA, US
Raghu Chalasani - San Jose CA, US
Akira Fujimura - Saratoga CA, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 11, 716 9, 716 12, 716 18
Abstract:
The present invention introduces methods, systems, and architectures for routing clock signals in an integrated circuit layout. The introduced clock signal clock signal structures are rendered with non Manhattan routing. In a first embodiment, the traditional recursive H clock signal structure is rendered after transforming the coordinates system such that a rotated recursive H clock signal structure is rendered. In another embodiment, a recursive Y structure is used to create a clock signal structure. The recursive Y structure may also be implemented in a rotated alignment. For clock signal redundancy, non Manhattan wiring may be used to create a clock signal mesh network.
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Raghu P Chalasani from San Jose, CA, age ~64 Get Report