Search

Porshia S Wrschka

from Phoenix, AZ
Age ~52
Get Report
Also known as:
Porshia S Parkinson, Peter T Wrschka, Porsh Parkinson, Rischka W Peter, Porsha A
Connected to:
Adam J Wrubel, 35Anthony C Wrubel, 53Jeff A Wrubel, 55Joseph J Wrubel, 46Kim M Wrubel, 60Lee R Wrubel, 60Myra G Wrubel, 87Shawn Wrubel, 64Todd A Wrubel, 53Dena R Wruble, 54

Porshia Wrschka Phones & Addresses

  • Phoenix, AZ
  • Danbury, CT
  • Tempe, AZ
  • Wappingers Falls, NY
  • Cambridge, MA

Resumes

Resumes

Porshia Wrschka Photo 1

Porshia Wrschka

View page
Location:
Phoenix, AZ
Industry:
Semiconductors
Work:
Ibm 2006 - 2007
Project Manager
Ibm 2000 - 2002
Process Development Engineer
Hp 1994 - 1994
Executive Sales Team Intern
Education:
The University of Texas at Austin 1995 - 2000
Doctorates, Doctor of Philosophy, Chemical Engineering, Philosophy Massachusetts Institute of Technology 1991 - 1995
Bachelors, Chemical Engineering Stuyvesant High School
Skills:
Ic
Semiconductors
Program Management
Design of Experiments
Semiconductor Industry
Cross Functional Team Leadership
Thin Films
Cmos
Process Engineering
Failure Analysis
Project Management
R&D
Interests:
Social Services
Children
Civil Rights and Social Action
Education
Environment
Science and Technology
Languages:
English
German
Certifications:
License 909326
License 2070880
Design For Six Sigma
Management and Strategy Institute, License 909326
Management and Strategy Institute, License 2070880
Management and Strategy Institute
Project Management Professional
Six Sigma Green Belt Certified
Porshia Wrschka Photo 2

Porshia Wrschka

View page

Business Records

Name / Title
Company / Classification
Phones & Addresses
Porshia Wrschka
WRSCHKA HOLDINGS LLC
2741 E Windmere Dr, Phoenix, AZ 85048

Publications

Us Patents

Sacrificial Collar Method For Improved Deep Trench Processing

View page
US Patent:
6905944, Jun 14, 2005
Filed:
May 8, 2003
Appl. No.:
10/249798
Inventors:
Michael Patrick Chudzik - Beacon NY, US
Irene McStay - Hopewell Junction NY, US
Helmut Horst Tews - Munich, DE
Porshia Shane Wrschka - Danbury CT, US
Assignee:
International Business Machines Corporation - Armonk NY
Infineon Technologies AG - Munich
International Classification:
H01L021/76
US Classification:
438435, 438242, 438244, 438245, 438259, 438246, 257330, 257331
Abstract:
A method for fabricating a deep trench etched into a semiconductor substrate is provided by the present invention. The trench is divided into an upper portion and a lower portion and the method allows for the lower portion to be processed differently from the upper portion. After the trench is etched into the semiconductor substrate, a nitride layer is formed over a sidewall of the trench. A layer of oxide is then formed over the nitride layer. A filler material is then deposited and recessed to cover the oxide layer in the lower portion of the trench, followed by the removal of the oxide layer from the upper portion of the trench above the filler material. Once the oxide layer is removed from the upper portion of the trench, the filler material can also be removed, while allowing the oxide layer and the nitride layer to remain in the lower portion of the trench. Silicon is selectively deposited on the exposed nitride layer in the upper portion of the trench. The oxide layer and the nitride layer is then removed from the lower portion.

Structure And Method Of Forming A Notched Gate Field Effect Transistor

View page
US Patent:
6905976, Jun 14, 2005
Filed:
May 6, 2003
Appl. No.:
10/249771
Inventors:
Jochen Beintner - Wappingers Falls NY, US
Yujun Li - Poughkeepsie NY, US
Naim Moumen - Wappingers Falls NY, US
Porshia Shane Wrschka - Danbury CT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L021/302
US Classification:
438752, 438739, 438933, 438592, 257401, 257616, 257407
Abstract:
The structure and method of forming a notched gate MOSFET disclosed herein addresses such problems as device reliability. A gate dielectric (e. g. gate oxide) is formed on the surface of an active area on the semiconductor substrate, preferably defined by an isolation trench region. A layer of polysilicon is then deposited on the gate dielectric. This step is followed by depositing a layer of silicon germanium) (SiGe). The sidewalls of the polysilicon layer are then laterally etched, selective to the SiGe layer to create a notched gate conductor structure, with the SiGe layer being broader than the underlying polysilicon layer. Sidewall spacers are preferably formed on sidewalls of the SiGe layer and the polysilicon layer. A silicide layer is preferably formed as a self-aligned silicide from a polysilicon layer deposited over the SiGe layer, to reduce resistance of the gate conductor. One or more other processing steps (e. g.

Method Of Forming A Collar Using Selective Sige/Amorphous Si Etch

View page
US Patent:
6987042, Jan 17, 2006
Filed:
May 30, 2003
Appl. No.:
10/250046
Inventors:
Jochen Beintner - Wappingers Falls NY, US
Naim Moumen - Austin TX, US
Porshia S. Wrschka - Danbury CT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/8242
US Classification:
438241, 438242, 438243, 438386
Abstract:
A method of forming collar isolation for a trench storage memory cell structure is provided in which amorphous Si (a:Si) and silicon germanium (SiGe) are first formed into a trench structure. An etching process that is selective to a:Si as compared to SiGe is employed in defining the regions in which the collar isolation will be formed. The selective etching process employed in the present invention is a wet etch process that includes etching with HF, rinsing, etching with NHOH, rinsing, and drying with a monohydric alcohol such as isopropanol. The sequence of NHOH etching and rinsing may be repeated any number of times. The conditions used in the selective etching process of the present invention are capable of etching a:Si at a faster rate than SiGe.

Self-Aligned Selective Hemispherical Grain Deposition Process And Structure For Enhanced Capacitance Trench Capacitor

View page
US Patent:
7101768, Sep 5, 2006
Filed:
Sep 27, 2002
Appl. No.:
10/260053
Inventors:
Porshia Shane Wrschka - Danbury CT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/20
US Classification:
438388, 438243, 438245, 438386
Abstract:
As disclosed herein, a method is provided, in an integrated circuit, for forming an enhanced capacitance trench capacitor. The method includes forming a trench in a semiconductor substrate and forming an isolation collar on a sidewall of the trench. The collar has at least an exposed layer of oxide and occupies only a “collar” portion of the sidewall, while a “capacitor” portion of the sidewall is free of the collar. A seeding layer is then selectively deposited on the capacitor portion of the sidewall. Then, hemispherical silicon grains are deposited on the seeding layer on the capacitor portion of the sidewall. A dielectric material is deposited, and then a conductor material, in that order, over the hemispherical silicon grains on the capacitor portion of the sidewall.

Structure And Method Of Forming A Notched Gate Field Effect Transistor

View page
US Patent:
7129564, Oct 31, 2006
Filed:
Feb 17, 2005
Appl. No.:
11/059819
Inventors:
Jochen Beintner - Wappingers Falls NY, US
Yujun Li - Poughkeepsie NY, US
Naim Moumen - Austin TX, US
Porshia Shane Wrschka - Danbury CT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 31/117
US Classification:
257616, 257 19, 257192, 257412, 257E21198, 257E21205
Abstract:
The structure and method of forming a notched gate MOSFET disclosed herein addresses such problems as device reliability. A gate dielectric (e. g. gate oxide) is formed on the surface of an active area on the semiconductor substrate, preferably defined by an isolation trench region. A layer of polysilicon is then deposited on the gate dielectric. This step is followed by depositing a layer of silicon germanium) (SiGe). The sidewalls of the polysilicon layer are then laterally etched, selective to the SiGe layer to create a notched gate conductor structure, with the SiGe layer being broader than the underlying polysilicon layer. Sidewall spacers are preferably formed on sidewalls of the SiGe layer and the polysilicon layer. A silicide layer is preferably formed as a self-aligned silicide from a polysilicon layer deposited over the SiGe layer, to reduce resistance of the gate conductor. One or more other processing steps (e. g.

Method Of Area Enhancement In Capacitor Plates

View page
US Patent:
6709947, Mar 23, 2004
Filed:
Dec 6, 2002
Appl. No.:
10/314548
Inventors:
Porshia S. Wrschka - Danbury CT
Irene McStay - Hopewell Junction NY
Assignee:
International Business Machines Corporation - Armonk NY
Infineon Technologies AG - Munich
International Classification:
H01L 2120
US Classification:
438398, 438964
Abstract:
A method and structure for increasing the area and capacitance of both trench and planar integrated circuit capacitors uses Si nodules deposited on a thin dielectric seeding layer that is absorbed during subsequent thermal processing, thereby avoiding a high resistance layer in the capacitor.
Control profile
Porshia S Wrschka from Phoenix, AZ, age ~52 Get Report