Resumes
Resumes
Logic Design Manager, Hardware Engineering
View pageLocation:
San Francisco, CA
Industry:
Semiconductors
Work:
Intel Corporation - Santa Clara, California Area since Jun 1997
Senior Staff Engineer
Senior Staff Engineer
Education:
University of Minnesota-Twin Cities
Ph.D., Electrical Engineering UC santa Barbara
MS, Electrical Engineering and Computer Science National Chiao Tung University
BS, Computer Engineering
Ph.D., Electrical Engineering UC santa Barbara
MS, Electrical Engineering and Computer Science National Chiao Tung University
BS, Computer Engineering
Skills:
Static Timing Analysis
Asic
Soc
Low Power Design
Eda
Verilog
Physical Design
Timing Closure
Formal Verification
Logic Synthesis
Logic Design
Systemverilog
Vlsi
Processors
Rtl Design
Power Analysis
Cad
Clocking
Application Specific Integrated Circuits
System on A Chip
Very Large Scale Integration
Cpu Design
Fpga Prototyping
Asic
Soc
Low Power Design
Eda
Verilog
Physical Design
Timing Closure
Formal Verification
Logic Synthesis
Logic Design
Systemverilog
Vlsi
Processors
Rtl Design
Power Analysis
Cad
Clocking
Application Specific Integrated Circuits
System on A Chip
Very Large Scale Integration
Cpu Design
Fpga Prototyping
Certifications:
Introduction To Finance
An Introduction To Interactive Programming In Python
An Introduction To Financial Accounting
Computational Investing, Part I
Coursera
An Introduction To Interactive Programming In Python
An Introduction To Financial Accounting
Computational Investing, Part I
Coursera