Pierre Malinge

20120086082, Apr 12, 2012

Oct 7, 2010

12/899663

PIERRE MALINGE - Beacon NY, US
JACK M. HIGMAN - Austin TX, US
SANJAY R. PARIHAR - Austin TX, US

H01L 21/70
H01L 21/8244

257368, 438197, 257E21661, 257E21532

A dual port static random access memory cell has pull-down transistors, pull-up transistors, and pass transistors. A first active region has a first pull-down transistor coupled to a true data node, a second pull-down transistor coupled to a complementary data node; a first pass transistor coupled to the true data node, and a second pass transistor coupled to the complementary data node. A second active region has the same size and shape as the first active region and has a third pull-down transistor coupled in parallel to the first-pull down transistor, a fourth pull-down transistor coupled in parallel to the second pull-down transistor; a third pass transistor coupled to the true data node, and a fourth pass transistor coupled to the complementary data node. A first pull-up transistor and a second pull-up transistor are located between the first and second active regions.

20130170275, Jul 4, 2013

Aug 22, 2012

13/591663

Shishir Kumar - Uttar Pradesh, IN
Dibya Dipti - Uttar Pradesh, IN
Pierre Malinge - Beacon NY, US

STMicroelectronics Pvt. Ltd. - Uttar Pradesh

G11C 5/06

365 63

A dual port SRAM has two data storage nodes, a true data and complementary data. A first pull down transistor has an active are that forms the drain region of the first transistor and the true data storage node that is physically isolated from all other transistor active areas of the memory cell. A second pull down transistor has an active area that form the drain region of a second transistor that is the complementary data node that is physically isolated from all other transistor active areas of the memory cell.