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Pierre J Aulagnier

from Sunnyvale, CA
Age ~66
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Also known as:
Pierr Aulagnier, Peirre Aulagnier
Phone and address:
1201 Robbia Dr, Sunnyvale, CA 94087
(408) 733-4469
Related to:
Mireille E Aulagnier, 63Alexandre Aulagnier, 32
Connected to:
Amarjit K Aulakh, 71Gurminder AulakhJagdev S Aulakh, 44Jamie J Aulakh, 44Kulwinder K Aulakh, 54Ranjit S Aulakh, 59Reet S Aulakh, 37Sukhwinder S Aulakh, 43Urminder S Aulakh, 62Roy F Aulaumea, 31

Pierre Aulagnier Phones & Addresses

  • 1201 Robbia Dr, Sunnyvale, CA 94087 (408) 733-4469
  • Cupertino, CA
  • San Jose, CA
  • Santa Clara, CA
  • 1201 Robbia Dr, Sunnyvale, CA 94087

Publications

Us Patents

Efficient Data Transfer Between Servers And Remote Peripherals

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US Patent:
20130138758, May 30, 2013
Filed:
Aug 9, 2005
Appl. No.:
11/200761
Inventors:
Ariel Cohen - Cupertino CA, US
Abhinav Anand - Milpitas CA, US
Pierre Aulagnier - Sunnyvale CA, US
Gerald Cheung - Palo Alto CA, US
Naveed Cochinwala - San Jose CA, US
Greg Lockwood - Redwood City CA, US
Ganesh Sundaresan - San Jose CA, US
Susheel Tadikonda - Santa Clara CA, US
Vikram Venkataraghavan - Santa Clara CA, US
Ming Wong - San Jose CA, US
International Classification:
H04L 29/08
US Classification:
709212
Abstract:
Methods and apparatus are provided for transferring data between servers and a remote entity having multiple peripherals. Multiple servers are connected to a remote entity over an Remote Direct Memory Access capable network. The remote entity includes peripherals such as network interface cards (NICs) and host bus adapters (HBAs). Server descriptor rings and descriptors are provided to allow efficient and effective communication between the servers and the remote entity.

Randomized Self-Checking Test System

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US Patent:
7334178, Feb 19, 2008
Filed:
Sep 9, 2005
Appl. No.:
11/222590
Inventors:
Pierre Aulagnier - Sunnyvale CA, US
Assignee:
Xsigo Systems - Sunnyvale CA
International Classification:
H03M 13/00
H04L 9/00
G06F 11/30
US Classification:
714758, 714776, 714786, 713160, 713190
Abstract:
Methods and apparatus are provided for verifying and validating operation of a design under test (DUT). Input data sequences having information used to check expected outputs are provided to a DUT. The input data sequences include checking headers and data. The checking headers and data are randomized using encryption to verify and validate operation of the DUT on a variety of bit sequences. Different keys are used to allow further scrambling.
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Pierre J Aulagnier from Sunnyvale, CA, age ~66 Get Report