Petru V Lauric

20130283020, Oct 24, 2013

Apr 18, 2012

13/449411

Robert N. Ehrlich - Round Rock TX, US
Petru Lauric - Medford MA, US
Robert A. McGowan - Cedar Park TX, US

FREESCALE SEMICONDUCTOR, INC. - Austin TX

G06F 9/30

712226, 712E09016

A program trace data compression mechanism in which execution of a variable length execution set (VLES) including multiple non-branch conditional instructions are traced in real-time in a manner that allows the instruction execution to be reconstructed completely by correlating the trace data with the traced binary code.

20170104653, Apr 13, 2017

Dec 17, 2015

14/972955

- AUSTIN TX, US
PETRU LAURIC - MEDFORD MA, US

H04L 12/26
H04L 12/24

A mechanism is provided for debugging of system-wide packet loss issues in network devices by automatically identifying packet loss conditions at runtime of the network device and by logging and analyzing relevant data to help diagnose the issues resulting in lost packets. A network programmer defines a path through the communications processor that identified packets should follow, and then hardware mechanisms within the modules of the communications processor are used to determine whether the packets are indeed following the defined path. If not, then the hardware mechanisms halt processing and logging being performed by all or part of the communications processor and provide logged information and packet information to an analysis tool for display. In this manner, debugging information can be provided in real time, along with a history of the packet's progress through the communication processor stages.

20150234582, Aug 20, 2015

Apr 15, 2014

14/253427

DRAGOS ADRIAN BADEA - BUCHAREST, RO
PETRU LAURIC - MEDFORD MA, US

FREESCALE SEMICONDUCTOR, INC. - Austin TX

G06F 3/0484
G06F 11/26

A debug configuration tool for configuration of on-chip debug features comprises a database comprising predefined analysis points, each relating to a configurable chip entity, and comprising a configurable condition and a configurable action for the chip entity, a plurality of predefined analysis groups, each relating to a group of configurable chip entities, and comprising a configurable condition and a configurable action for the group of chip entities. The tool comprises a graphical user interface module arranged to display representations of at least some of the analysis points and the analysis groups on different levels of detail, and to receive input from a user to set the configurable conditions and/or actions for the displayed analysis points and the analysis groups. An application program interface module processes data received from the graphical user interface module to obtain debug settings and to communicate the debug settings to a debug target system configuration module.