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Perry Willmann Remaklus

from Raleigh, NC
Age ~59
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Also known as:
Perry W Remaklus, Perry B Remaklus, Willmann Remaklus Perry
Phone and address:
5313 Inglewood Ln, Raleigh, NC 27609
(919) 781-2483
Related to:
Connor Schaad, 30Carl SchaadCarlton SchaadCassandra Schaad, 28
Connected to:
Donna M Remaklus, 72Miranda L Remaklus, 45Srilata Remala, 40Adam M Remaley, 40Andrew J Remaley, 73Anthony T Remaley, 64Michael J Remaley, 52Gary A Remar, 72Paul R Remark, 70Vince I Remata, 60

Perry Remaklus Phones & Addresses

  • 5313 Inglewood Ln, Raleigh, NC 27609 (919) 781-2483
  • North Chesterfield, VA
  • Dundee, MI
  • Blacksburg, VA

Work

Company: Willmann-bell Position: President and publisher

Education

Degree: High school graduate or higher

Skills

Editing

Industries

Publishing

Resumes

Resumes

Perry Remaklus Photo 1

President And Publisher

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Location:
Richmond, VA
Industry:
Publishing
Work:
Willmann-Bell
President and Publisher
Skills:
Editing

Business Records

Name / Title
Company / Classification
Phones & Addresses
Perry Remaklus
President
Willman-Bell Inc
Business Consulting Services · Business Service
11480 Robious Rd, Richmond, VA 23235
PO Box 35025, Richmond, VA 23235
(804) 320-7016

Publications

Us Patents

Method And System For Providing Directed Bank Refresh For Volatile Memories

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US Patent:
20050265102, Dec 1, 2005
Filed:
Nov 5, 2004
Appl. No.:
10/982038
Inventors:
Perry Remaklus - Raleigh NC, US
Robert Walker - Raleigh NC, US
International Classification:
G11C007/00
US Classification:
365222000
Abstract:
A memory system is provided. The memory system includes a volatile memory having a number of banks and a memory controller configured to control the volatile memory to engage in an auto-refresh mode or a self-refresh mode. The memory controller is further configured to direct the volatile memory to perform an auto-refresh operation on a target bank. The remaining banks are available for access while the auto-refresh operation is being performed on the target bank.

Method And System For Providing Seamless Self-Refresh For Directed Bank Refresh In Volatile Memories

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US Patent:
20050265103, Dec 1, 2005
Filed:
Nov 5, 2004
Appl. No.:
10/982277
Inventors:
Perry Remaklus - Raleigh NC, US
Robert Walker - Raleigh NC, US
International Classification:
G11C007/00
US Classification:
365222000
Abstract:
A memory system is provided. The system includes a volatile memory having a number of banks and configured to engage in one of a number of operating modes including an auto-refresh mode and a self-refresh mode, and a memory controller configured to direct the volatile memory to engage in one of the operating modes. Upon the memory controller directing the volatile memory to engage in the self-refresh mode, the memory controller is further configured to provide an entry bank address to the volatile memory, the entry bank address corresponding to the first bank that is to be refreshed during the self-refresh mode. Upon the volatile memory exiting the self-refresh mode, the volatile memory is further configured to make an exit bank address available to the memory controller, the exit bank address corresponding to the last bank that was refreshed prior to the volatile memory exiting the self-refresh mode.

Method And System For Providing Independent Bank Refresh For Volatile Memories

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US Patent:
20050265104, Dec 1, 2005
Filed:
Nov 5, 2004
Appl. No.:
10/982691
Inventors:
Perry Remaklus - Raleigh NC, US
Robert Walker - Raleigh NC, US
International Classification:
G11C007/00
US Classification:
365222000
Abstract:
A memory system is provided. The memory system includes a volatile memory having a number of banks, each bank having a number of rows, and a memory controller configured to direct the volatile memory to engage in an auto-refresh mode, the memory controller further configured to provide a target bank address to the volatile memory. The volatile memory is configured to perform an auto-refresh operation in the auto-refresh mode, the auto-refresh operation being performed on a target bank identified by the target bank address. Remaining banks in the plurality of banks other than the target bank are available for memory access while the auto-refresh operation is being performed on the target bank.

Refreshing Dynamic Volatile Memory

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US Patent:
20060002217, Jan 5, 2006
Filed:
Jun 10, 2005
Appl. No.:
11/150649
Inventors:
Robert Walker - Raleigh NC, US
Perry Remaklus - Raleigh NC, US
International Classification:
G11C 7/04
US Classification:
365211000
Abstract:
A memory system, and process for refreshing the memory, is disclosed. The memory system includes memory, a temperature sensor configured to measure the temperature of the memory, and a memory controller configured to refresh the memory at a refresh rate, the refresh rate being controlled as a function of the temperature measured by the temperature sensor.

Priority Scheme For Executing Commands In Memories

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US Patent:
20060112240, May 25, 2006
Filed:
Nov 24, 2004
Appl. No.:
10/997542
Inventors:
Robert Walker - Raleigh NC, US
Perry Remaklus - Raleigh NC, US
International Classification:
G06F 13/00
US Classification:
711154000
Abstract:
A command execution priority scheme for memories is disclosed. The priority scheme is directed to systems and techniques for storing and retrieving data from memory. A command queue may be used to receive a plurality of commands, each of the commands requesting access to the memory. A command selector may be used to evaluate a block the of the commands in the command queue to select one of the commands from the block to execute, and execute the selected command.

Directed Auto-Refresh Synchronization

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US Patent:
20060143372, Jun 29, 2006
Filed:
Apr 27, 2005
Appl. No.:
11/115915
Inventors:
Robert Walker - Raleigh NC, US
Perry Remaklus - Raleigh NC, US
International Classification:
G06F 13/28
US Classification:
711106000
Abstract:
In a directed auto-refresh (DARF) mode, refresh commands are issued by a controller, and refresh row and bank addresses are maintained internally to a memory module. A bank address counter internal to the memory is initialized to a first predetermined value upon entering DARF mode. The memory refreshes the currently addressed bank in response to a DARF command, and increments the bank address counter in a predetermined sequence. The controller tracks the bank address, and may issue one or more memory access commands while a DARF operation is being performed, if the memory access and the refresh are directed to different banks. Upon exiting a self-refresh mode, the bank address counter assumes a second predetermined value. The second predetermined value may be fixed, or may be n+1, where n is the value of the bank address counter when self-refresh mode is initiated.

Method And Apparatus Of Reducing Transfer Latency In An Soc Interconnect

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US Patent:
20060149874, Jul 6, 2006
Filed:
Dec 30, 2004
Appl. No.:
11/027532
Inventors:
J. Prakash Subramaniam Ganasan - Youngsville NC, US
Perry Willmann Remaklus - Raleigh NC, US
International Classification:
G06F 13/00
US Classification:
710110000
Abstract:
Embodiments of the invention are directed to a method and apparatus for reducing transfer latency in a system on a chip, the system on a chip comprising a bus master, a bus slave and an arbiter, wherein the bus master, bus slave and arbiter are in electronic communication therebetween. A request is transmitted from the bus master to the arbiter, wherein a priority signal is associated with a latency requirement. The arbiter reviews the latency requirement prior to transmitting the request to the bus slave and determines whether to elevate the priority signal. The request signal is then transmitted from the arbiter to the bus slave. The bus slave fulfills the request and transmits a response to the request, wherein the transmission includes the priority signal.

Flow Control Method To Improve Bus Utilization In A System-On-A-Chip Integrated Circuit

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US Patent:
20060179192, Aug 10, 2006
Filed:
Feb 10, 2005
Appl. No.:
11/055922
Inventors:
J. Prakash Ganasan - Youngsville NC, US
Perry Remaklus - Raleigh NC, US
International Classification:
G06F 13/00
US Classification:
710110000
Abstract:
A system-on-chip (SoC) integrated circuit (IC) has reduced bus contention and improved bus utilization. The SoC IC includes a bus controller. Masters interconnected with the bus controller issue requests for data and receive requested data in response to the requests. Slaves interconnected with the bus controller receive the requests for data and provide the requested data to the requesting masters. Control signals issued by the bus controller indicate to each slave which masters are not ready to receive the data it requested from that slave. The slaves delay transferring data to any masters that are not ready for the requested data, and provide data to different masters that are ready to receive the data they requested from the slaves.
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Perry Willmann Remaklus from Raleigh, NC, age ~59 Get Report