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Peicheng D Ju

from Berkeley Heights, NJ
Age ~67
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Also known as:
Pei Cheng Ju, Pei-Cheng Ju, Peiching Ju, Peicheng Lu, Ju Peicheng
Phone and address:
110 Cedar Green Ln, Berkeley Heights, NJ 07922
(908) 490-0355
Related to:
Sanghoon Kim, 51Myungsook Kim, 56Sun Lei, 51Joo Y Kim, 54Jiyoung Kim, 59
Connected to:
Bong L Ju, 40Clara D Ju, 86De B Ju, 58Franklin D Ju, 66Hanna Y Ju, 41Harry Ju, 48Hester H Ju, 61Jack S Ju, 59Jang B Ju, 88Jay L Ju, 77

Peicheng Ju Phones & Addresses

  • 110 Cedar Green Ln, Berkeley Hts, NJ 07922 (908) 490-0355 (908) 322-1450
  • Berkeley Heights, NJ
  • New York, NY
  • 10 Risk Ave, Summit, NJ 07901 (908) 273-8754
  • Grass Valley, CA
  • Rockville, MD
  • Union, NJ
  • 110 Cedar Green Ln, Berkeley Heights, NJ 07922 (908) 510-7192

Work

Position: Professional/Technical

Education

Degree: High school graduate or higher

Resumes

Resumes

Peicheng Ju Photo 1

Engineer

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Location:
1901 Main St, Irvine, CA 92614
Industry:
Semiconductors
Work:
Conexant
Engineer
Peicheng Ju Photo 2

Director, Ams Designs

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Location:
New York, NY
Industry:
Semiconductors
Work:
Conexant Jun 2003 - Aug 2009
High-Speed Ams Design Manager
Ikanos Communications Jun 2003 - Aug 2009
Director, Ams Designs
Education:
Columbia University In the City of New York
Doctorates, Doctor of Philosophy, Electrical Engineering, Philosophy
Skills:
Semiconductors

Publications

Us Patents

Use Of Current Folding To Improve The Performance Of A Current -Steered Dac Operating At Low Supply Voltage

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US Patent:
6518906, Feb 11, 2003
Filed:
Jul 16, 2001
Appl. No.:
09/906162
Inventors:
Christopher J Abel - Coplay PA
Joseph Anidjar - Asbury NJ
Peicheng Ju - Berkeley Heights NJ
Assignee:
Agere Systems Guardian Corp. - Orlando FL
International Classification:
H03M 166
US Classification:
341144, 341119, 236115
Abstract:
The performance of a single-bit cell in a DAC is improved by decoupling the voltage swing across the load resistors from the output of the current steering device. This can be achieved by providing for a single-bit cell having a first load resistor R and a second load resistor R a current steering circuit, and a decoupling circuit operably coupled between the current steering circuit and the resistors R R The current steering circuit steers at least part of a current I through a circuit path towards either the first resistor R or the second resistor R The decoupling circuit decouples voltage swings across the load resistors R R from the current steering circuit.

Low Voltage Bandgap Reference Circuit

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US Patent:
6531857, Mar 11, 2003
Filed:
Nov 8, 2001
Appl. No.:
10/007913
Inventors:
Peicheng Ju - Berkeley Heights NJ
Assignee:
Agere Systems, Inc. - Berkeley Heights NJ
International Classification:
G05F 316
US Classification:
323316, 327538
Abstract:
A bandgap reference circuit that uses reduced substrate area while requiring relatively low voltage. The circuit may include a bipolar transistor with a resistor electrically connected across the emitter-base of the bipolar transistor. The resistor sums a first current with a second current and also generates a fractional V. The bandgap reference circuit may have a first current proportional to V , and a second current proportional to a PTAT current. An impedance booster may be incorporated into the circuit. Also disclosed is a method of regulating a voltage level using embodiments of the bandgap reference circuit.

Five-Level Switched-Capacitor Dac, Method Of Operation Thereof And Sigma-Delta Converter Employing The Same

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US Patent:
60812184, Jun 27, 2000
Filed:
Jan 30, 1998
Appl. No.:
9/016613
Inventors:
Peicheng Ju - Summit NJ
Krishnaswamy Nagaraj - Somerville NJ
Assignee:
Lucent Technologies, Inc. - Murray Hill NJ
International Classification:
H03M 166
H03M 300
US Classification:
341150
Abstract:
A digital-to-analog converter (DAC) and a method of converting digital numbers to analog equivalents. In one embodiment, the DAC includes: (1) a data decoder that receives a digital number and an input clock signal and develops therefrom SIGN and M control signals and complementary. phi. sub. 1 and. phi. sub. 2 clock signals and (2) a conversion circuit, coupled to the data decoder and including first and second operational amplifiers (op amps), a switching circuit and sampling and integrating capacitors, the switching circuit coupling positive and negative reference voltages to the sampling capacitors as a function of states of the SIGN and M control signals and adjusting feedback loops associated with the first and second op amps as a function of states of the. phi. sub. 1 and. phi. sub. 2 clock signals, the first and second op amps generating a voltage difference at outputs thereof representing an analog equivalent of the digital number.
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Peicheng D Ju from Berkeley Heights, NJ, age ~67 Get Report