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Pawel Osciak Phones & Addresses

  • Santa Clara, CA

Work

Company: Google Oct 2011 Address: Tokyo, Japan Position: Software engineer

Education

Degree: Master of Science School / High School: Politechnika Warszawska 2004 to 2010 Specialities: Computer Information System Engineering

Skills

Embedded Systems • Linux • Linux Kernel • Open Source • Device Drivers • Operating Systems • Computer Architecture • Memory Management • Digital Electronics • Version Control • Web Design • Hardware Virtualization • Kernel • Python • Perl • C • C++ • Microcontrollers • Subversion • Software Engineering • Git • OOP • Embedded Linux

Languages

English • Polish • Japanese • Russian

Awards

Master's thesis with honors

Interests

Japanese language, culture and cuisine. ...

Industries

Computer Software

Resumes

Resumes

Pawel Osciak Photo 1

Software Engineer At Google

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Position:
Software Engineer at Google, Linux kernel hacker and maintainer at Linux kernel
Location:
Within 23 wards, Tokyo, Japan
Industry:
Computer Software
Work:
Google - Tokyo, Japan since Oct 2011
Software Engineer

Linux kernel since Feb 2009
Linux kernel hacker and maintainer

Intel Corporation Oct 2010 - Oct 2011
Software Engineer

Samsung Electronics Nov 2008 - Oct 2010
Linux kernel graphics CoE leader

Sanyo Jan 2008 - Aug 2008
Intern at R&D HQ, Osaka, Japan
Education:
Politechnika Warszawska 2004 - 2010
Master of Science, Computer Information System Engineering
Skills:
Embedded Systems
Linux
Linux Kernel
Open Source
Device Drivers
Operating Systems
Computer Architecture
Memory Management
Digital Electronics
Version Control
Web Design
Hardware Virtualization
Kernel
Python
Perl
C
C++
Microcontrollers
Subversion
Software Engineering
Git
OOP
Embedded Linux
Interests:
Japanese language, culture and cuisine. Linux kernel, operating systems, computer architecture, embedded systems. Reading, photography (especially urban and night, HDR), playing the piano. Sports: bridge, volleyball, sailing, skiing.
Honor & Awards:
Master's thesis with honors
Languages:
English
Polish
Japanese
Russian

Publications

Us Patents

Hardware Profiling Mechanism To Enable Page Level Automatic Binary Translation

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US Patent:
20130311758, Nov 21, 2013
Filed:
Mar 30, 2012
Appl. No.:
13/993792
Inventors:
Paul Caprioli - Hillsboro OR, US
Matthew C. Merten - Hillsboro OR, US
Muawya M. Al-Otoom - Beaverton OR, US
Omar M. Shaikh - Portland OR, US
Abhay S. Kanhere - Fremont CA, US
Suresh Srinivas - Portland OR, US
Koichi Yamada - Los Gatos CA, US
Vivek Thakkar - Sunnyvale CA, US
Pawel Osciak - Santa Clara CA, US
International Classification:
G06F 9/38
US Classification:
712233
Abstract:
A hardware profiling mechanism implemented by performance monitoring hardware enables page level automatic binary translation. The hardware during runtime identifies a code page in memory containing potentially optimizable instructions. The hardware requests allocation of a new page in memory associated with the code page, where the new page contains a collection of counters and each of the counters corresponds to one of the instructions in the code page. When the hardware detects a branch instruction having a branch target within the code page, it increments one of the counters that has the same position in the new page as the branch target in the code page. The execution of the code page is repeated and the counters are incremented when branch targets fall within the code page. The hardware then provides the counter values in the new page to a binary translator for binary translation.

Hardware Profiling Mechanism To Enable Page Level Automatic Binary Translation

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US Patent:
20170212825, Jul 27, 2017
Filed:
Jan 10, 2017
Appl. No.:
15/403120
Inventors:
- Santa Clara CA, US
Matthew C. Merten - Hillsboro OR, US
Muawya M. Al-Otoom - Beaverton OR, US
Omar M. Shaikh - Portland OR, US
Abhay S. Kanhere - Fremont CA, US
Suresh Srinivas - Portland OR, US
Koichi Yamada - Los Gatos CA, US
Vivek Thakkar - Sunnyvale CA, US
Pawel Osciak - Santa Clara CA, US
International Classification:
G06F 11/34
G06F 9/455
G06F 11/36
G06F 11/07
G06F 9/45
Abstract:
A hardware profiling mechanism implemented by performance monitoring hardware enables page level automatic binary translation. The hardware during runtime identifies a code page in memory containing potentially optimizable instructions. The hardware requests allocation of a new page in memory associated with the code page, where the new page contains a collection of counters and each of the counters corresponds to one of the instructions in the code page. When the hardware detects a branch instruction having a branch target within the code page, it increments one of the counters that has the same position in the new page as the branch target in the code page. The execution of the code page is repeated and the counters are incremented when branch targets fall within the code page. The hardware then provides the counter values in the new page to a binary translator for binary translation.
Pawel L Osciak from Santa Clara, CA, age ~41 Get Report