Pavel O Fastenko

7151028, Dec 19, 2006

Nov 4, 2004

10/981174

Shenqing Fang - Fremont CA, US
Rinji Sugino - San Jose CA, US
Kuo-Tung Chang - Saratoga CA, US
Zhigang Wang - Sunnyvale CA, US
Kazuhiro Mizutani - Sunnyvale CA, US
Pavel Fastenko - Sunnyvale CA, US

Spansion LLC - Sunnyvale CA

H01L 21/26

438257, 438201, 438303, 438305, 438306, 438593

According to one exemplary embodiment, a method for fabricating a floating gate memory cell on a substrate comprises a step of forming a first spacer adjacent to a source sidewall of a stacked gate structure, where the stacked gate structure is situated over a channel region in the substrate. The method further comprises forming a high energy implant doped region adjacent to the first spacer in a source region of the substrate. The method further comprises forming a recess in the source region, where a sidewall of the recess is situated adjacent to a source of the floating gate memory cell, and where forming the recess comprises removing the first spacer. The method further comprises forming a second spacer adjacent to the source sidewall of the stacked gate structure, where the second spacer extends to a bottom of the recess, and where the second spacer comprises plasma-grown oxide.

7170130, Jan 30, 2007

Aug 11, 2004

10/915771

Shenqing Fang - Fremont CA, US
Kuo-Tung Chang - Saratoga CA, US
Pavel Fastenko - Sunnyvale CA, US
Zhigang Wang - Sunnyvale CA, US

Spansion LLC - Sunnyvale CA

H01L 29/788

257316, 438259, 257E21179

According to one exemplary embodiment, a method for fabricating a floating gate memory cell on substrate comprises a step of forming a spacer adjacent to a source sidewall of a stacked gate structure, where the stacked gate structure is situated over a channel region in substrate. The method further comprises forming a high energy implant doped region adjacent to the spacer in the source region of substrate. The method further comprises forming a recess in a source region of the substrate, where the recess has a sidewall, a bottom, and a depth, and where the sidewall of the recess is situated adjacent to a source of the floating gate memory cell. According to this exemplary embodiment, the spacer causes the source to have a reduced lateral straggle and diffusion in the channel region, which causes a reduction in drain induced barrier lowering (DIBL) in the floating gate memory cell.

7488657, Feb 10, 2009

Jun 17, 2005

11/155707

Shenqing Fang - Fremont CA, US
Hiroyuki Ogawa - Sunnyvale CA, US
Kuo-Tung Chang - Saratoga CA, US
Pavel Fastenko - Sunnyvale CA, US
Kazuhiro Mizutani - Sunnyvale CA, US
Zhigang Wang - Sunnyvale CA, US

Spansion LLC - Sunnyvale CA

H01L 21/336

438289, 438257, 438258, 257128, 257202

Embodiments of the present invention disclose a memory device having an array of flash memory cells with source contacts that facilitate straight word lines, and a method for producing the same. The array is comprised of a plurality of non-intersecting shallow trench isolation (STI) regions that isolate a plurality of memory cell columns. A source column is implanted with n-type dopants after the formation of a tunnel oxide layer and a first polysilicon layer. The implanted source column is coupled to a plurality of common source lines that are coupled to a plurality of source regions associated with memory cells in the array. A source contact is coupled to the implanted source column for providing electrical coupling with the plurality of source regions. The source contact is collinear with a row of drain contacts that are coupled to drain regions associated with a row of memory cells. The arrangement of source contacts collinear with the row of drain contacts allows for straight word line formation.

7851306, Dec 14, 2010

Dec 3, 2008

12/327641

Shenqing Fang - Fremont CA, US
Hiroyuki Ogawa - Sunnyvale CA, US
Kuo-Tung Chang - Saratoga CA, US
Pavel Fastenko - Sunnyvale CA, US
Kazuhiro Mizutani - Sunnyvale CA, US
Zhigang Wang - Sunnyvale CA, US

Spansion LLC - Sunnyvale CA

H01L 21/336

438257, 438258, 438286, 257202, 257296

Embodiments of the present invention disclose a memory device having an array of flash memory cells with source contacts that facilitate straight word lines, and a method for producing the same. The array is comprised of a plurality of non-intersecting shallow trench isolation (STI) regions that isolate a plurality of memory cell columns. A source column is implanted with n-type dopants after the formation of a tunnel oxide layer and a first polysilicon layer. The implanted source column is coupled to a plurality of common source lines that are coupled to a plurality of source regions associated with memory cells in the array. A source contact is coupled to the implanted source column for providing electrical coupling with the plurality of source regions. The source contact is collinear with a row of drain contacts that are coupled to drain regions associated with a row of memory cells. The arrangement of source contacts collinear with the row of drain contacts allows for straight word line formation.

7029975, Apr 18, 2006

May 4, 2004

10/839561

Shenqing Fang - Fremont CA, US
Kuo-Tung Chang - Saratoga CA, US
Pavel Fastenko - Sunnyvale CA, US
Kazuhiro Mizutani - Sunnyvale CA, US

Advanced Mirco Devices, Inc. - Sunnyvale CA

H01L 21/336

438258, 438286

A method and apparatus for coupling to a source line is disclosed. A semiconductor structure having an array of memory cells arranged in rows and columns is described. The array of memory cells includes a source region that is implanted with n-type dopants isolated between an adjoining pair of the non-intersecting STI regions and isolated from a drain region during the implantation. A source contact is located along a row of drain contacts that are coupled to drain regions of a row of memory cells and the source contact is coupled to the source region for providing electrical coupling with a plurality of source lines. The isolating of the implanted source region from the drain region during the implanting enables coupling of the source contact to the source lines while maintaining the n-type dopants between the STI regions and avoiding lateral diffusion to a bit-line.