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Paul A Papworth

from Linwood, MI
Age ~52
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Also known as:
Paul Andrew Papworth, Paul Papaworth
Related to:
Gary James Brand, 69Charles Richard Papworth, 54Kyle A Papworth, 43Katie E Legner, 43Drew M Papworth, 38Skip PapworthMargaret Y Papworth, 76
Connected to:
Christine M Papworth, 74Hugh R Papy, 68Corey D Paquay, 36David L Paquay, 66Diana M Paque, 76Kurt A Paque, 56Shafer Paque, 38Roland Paqueo, 50Michael Paquereau, 67Alice D Paquet, 54

Paul Papworth Phones & Addresses

  • Linwood, MI
  • 4050 Maloney Rd, Pinconning, MI 48650 (989) 879-5742
  • Pleasant Valley, NY
  • 120 Market St, Wappingers Falls, NY 12590 (845) 298-8980
  • 1547 Hagadorn Rd, East Lansing, MI 48823 (517) 351-0853
  • Lansing, MI
  • Novi, MI
  • Belleville, MI
  • San Marcos, TX
  • 4050 Maloney Rd, Pinconning, MI 48650

Publications

Us Patents

Ultra-Thin Soi Vertical Bipolar Transistors With An Inversion Collector On Thin-Buried Oxide (Box) For Low Substrate-Bias Operation And Methods Thereof

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US Patent:
7375410, May 20, 2008
Filed:
Feb 25, 2004
Appl. No.:
10/787002
Inventors:
Herbert L. Ho - New Windsor NY, US
Mahender Kumar - Fishkill NY, US
Qiqing Ouyang - Yorktown Heights NY, US
Paul A. Papworth - Wappingers Falls NY, US
Christopher D. Sheraw - Wappingers Falls NY, US
Michael D. Steigerwalt - Newburgh NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 27/102
US Classification:
257526, 257587, 257592, 257E29183, 257E2919, 257E29198
Abstract:
The present invention provides a “collector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped collector. Instead, the inventive vertical SOI BJT uses a back gate-induced, minority carrier inversion layer as the intrinsic collector when it operates. In accordance with the present invention, the SOI substrate is biased such that an inversion layer is formed at the bottom of the base region serving as the collector. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS.

Method Of Fabricating A Vertical Bipolar Transistor With A Majority Carrier Accumulation Layer As A Subcollector For Soi Bicmos With Reduced Buried Oxide Thickness

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US Patent:
7485537, Feb 3, 2009
Filed:
Jul 20, 2006
Appl. No.:
11/490326
Inventors:
Herbert L. Ho - New Windsor NY, US
Mahender Kumar - Fishkill NY, US
Qiqing Ouyang - Yorktown Heights NY, US
Paul A. Papworth - Wappingers Falls NY, US
Christopher D. Sheraw - Wappingers Falls NY, US
Michael D. Steigerwalt - Newburgh NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/331
H01L 21/8222
H01L 21/76
US Classification:
438309, 438311, 438312, 438313, 438342
Abstract:
The present invention provides a a method of fabricating bipolar junction transistors (BJTs) on selected areas of a very thin buried oxide (BOX) using a conventional silicon-on-insulator (SOI) starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS.

Vertical Bipolar Transistor With A Majority Carrier Accumulation Layer As A Subcollector For Soi Bicmos With Reduced Buried Oxide Thickness For Low-Substrate Bias Operation

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US Patent:
7691716, Apr 6, 2010
Filed:
Jun 24, 2008
Appl. No.:
12/144998
Inventors:
Herbert L. Ho - New Windsor NY, US
Mahender Kumar - Fishkill NY, US
Qiging Ouyang - Yorktown Heights NY, US
Paul A. Papworth - Wappingers Falls NY, US
Christopher D. Sheraw - Wappingers Falls NY, US
Michael D. Steigerwalt - Newburgh NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/331
H01L 21/8222
US Classification:
438309, 438311, 257E21372
Abstract:
The present invention provides a “subcollector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped subcollector. Instead, the inventive vertical SOI BJT uses a back gate-induced, majority carrier accumulation layer as the subcollector when it operates. The SOI substrate is biased such that the accumulation layer is formed at the bottom of the first semiconductor layer. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS. A back-gated CMOS device is also provided.

Ultra-Thin Soi Vertical Bipolar Transistors With An Inversion Collector On Thin-Buried Oxide (Box) For Low Substrate-Bias Operation And Methods Thereof

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US Patent:
7763518, Jul 27, 2010
Filed:
Apr 8, 2008
Appl. No.:
12/099437
Inventors:
Herbert L. Ho - New Windsor NY, US
Mahender Kumar - Fishkill NY, US
Qiqing Ouyang - Yorktown Heights NY, US
Paul A. Papworth - Wappingers Falls NY, US
Christopher D. Sheraw - Wappingers Falls NY, US
Michael D. Steigerwalt - Newburgh NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/331
US Classification:
438311, 438322, 257E21372, 257526
Abstract:
The present invention provides a “collector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped collector. Instead, the inventive vertical SOI BJT uses a back gate-induced, minority carrier inversion layer as the intrinsic collector when it operates. In accordance with the present invention, the SOI substrate is biased such that an inversion layer is formed at the bottom of the base region serving as the collector. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS.

Ultra-Thin Soi Vertical Bipolar Transistors With An Inversion Collector On Thin-Buried Oxide (Box) For Low Substrate-Bias Operation And Methods Thereof

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US Patent:
7911024, Mar 22, 2011
Filed:
Feb 17, 2010
Appl. No.:
12/707305
Inventors:
Herbert L. Ho - New Windsor NY, US
Mahender Kumar - Fishkill NY, US
Qiqing Ouyang - Yorktown Heights NY, US
Paul A. Papworth - Wappingers Falls NY, US
Christopher D. Sheraw - Wappingers Falls NY, US
Michael D. Steigerwalt - Newburgh NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 27/102
US Classification:
257526, 257587, 257592, 257E29183, 257E2919, 257E29198
Abstract:
The present invention provides a “collector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped collector. Instead, the inventive vertical SOI BJT uses a back gate-induced, minority carrier inversion layer as the intrinsic collector when it operates. In accordance with the present invention, the SOI substrate is biased such that an inversion layer is formed at the bottom of the base region serving as the collector. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS.

Vertical Bipolar Transistor With A Majority Carrier Accumulation Layer As A Subcollector For Soi Bicmos With Reduced Buried Oxide Thickness For Low-Substrate Bias Operation

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US Patent:
20060043530, Mar 2, 2006
Filed:
Sep 1, 2004
Appl. No.:
10/931855
Inventors:
Herbert Ho - New Windsor NY, US
Mahender Kumar - Fishkill NY, US
Qiqing Ouyang - Yorktown Heights NY, US
Paul Papworth - Wappingers Falls NY, US
Christopher Sheraw - Wappingers Falls NY, US
Michael Steigerwalt - Newburgh NY, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY
International Classification:
H01L 27/01
US Classification:
257565000
Abstract:
The present invention provides a “subcollector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped subcollector. Instead, the inventive vertical SOI BJT uses a back gate-induced, majority carrier accumulation layer as the subcollector when it operates. The SOI substrate is biased such that the accumulation layer is formed at the bottom of the first semiconductor layer. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS. A back-gated CMOS device is also provided.

Ultra-Thin Soi Vertical Bipolar Transistors With An Inversion Collector On Thin-Buried Oxide (Box) For Low Substrate-Bias Operation And Methods Thereof

View page
US Patent:
20080132025, Jun 5, 2008
Filed:
Oct 23, 2007
Appl. No.:
11/877305
Inventors:
Herbert L. Ho - New Windsor NY, US
Mahender Kumar - Fishkill NY, US
Qiqing Ouyang - Yorktown Heights NY, US
Paul A. Papworth - Wappingers Falls NY, US
Christopher D. Sheraw - Wappingers Falls NY, US
Michael D. Steigerwalt - Newburgh NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/331
US Classification:
438311, 257E21372
Abstract:
The present invention provides a “collector-less” silcon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped collector. Instead, the inventive vertical SOI BJT uses a back gate-induced, minority carrier inversion layer as the intrinsic collector when it operates. In accordance with the present invention, the SOI substrate is biased such that an inversion layer is formed at the bottom of the base region serving as the collector The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BIJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS.
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Paul A Papworth from Linwood, MI, age ~52 Get Report