US Patent:
20040252474, Dec 16, 2004
Inventors:
Hanjoo Na - Fremont CA, US
Myeongjin Shin - Fremont CA, US
Paul Heng - Fremont CA, US
International Classification:
G01R001/00
G05F001/00
H05K007/18
US Classification:
361/813000, 029/827000, 029/840000, 029/593000
Abstract:
A novel multi chip module having increased accuracy of the soldering the integrated circuits (ICs) is provided by utilizing two additional lead frames and turning over the first lead frame soldered IC and stacking secondary IC thereon. Arrays of the first lead frames are mounted on a top tray guided by tooling pins. Solder pastes are printed on the first lead frames. Arrays of the second lead frames are placed on the first lead frames guided with tooling pins. Another layer of solder pastes are printed on the second lead frames. Thermal conductive glue is dispensed on the central portions of the first lead frames. ICs, which become the “bottom ICs” later, are placed on the central portions of the first lead frames upside down by a pick/place machine. After heat treatment, inspection and repair, the bottom ICs are mounted in a pocket on a bottom tray facing the first lead frames upside. Another layer of solder pastes are printed on the first lead frames. Other ICs, which become the “top ICs”, are placed on the first lead frames. Secondary heat treatment, inspection and repairing procedures are executed. Exact position of the solder paste and leads of the IC's are matched by the pick/position machine. The noble structure of this invention enables maintaining the original ICs' characters without deforming at a high production rate.