Resumes
Resumes
Senior Design Verification Engineer
View pageLocation:
806 Saratoga Ave, San Jose, CA 95129
Industry:
Semiconductors
Work:
Cypress Semiconductor Corporation Jul 2018 - Oct 2018
Staff Verification Engineer
Xilinx Jul 2018 - Oct 2018
Senior Design Verification Engineer
Cypress Semiconductor Corporation Mar 2016 - Jul 2018
Verification Engineer at Cypress Semiconductor
Atmel Corporation Oct 2015 - Mar 2016
Ic Design Verification Engineer
Arasan Chip Systems Inc., Jun 2014 - Oct 2015
Junior Design Engineer
Staff Verification Engineer
Xilinx Jul 2018 - Oct 2018
Senior Design Verification Engineer
Cypress Semiconductor Corporation Mar 2016 - Jul 2018
Verification Engineer at Cypress Semiconductor
Atmel Corporation Oct 2015 - Mar 2016
Ic Design Verification Engineer
Arasan Chip Systems Inc., Jun 2014 - Oct 2015
Junior Design Engineer
Education:
San Jose State University 2013 - 2015
Master of Science, Masters, Electrical Engineering Lokmanya Tilak College of Engineering 2008 - 2012
Bachelor of Engineering, Bachelors, Electronics Engineering
Master of Science, Masters, Electrical Engineering Lokmanya Tilak College of Engineering 2008 - 2012
Bachelor of Engineering, Bachelors, Electronics Engineering
Skills:
Vlsi
Verilog
Embedded Systems
C++
Asic
Hardware Architecture
Systemverilog
Modelsim
Automation
Cadence Virtuoso
Perl Script
Perl
Embedded C
Fpga
Plc
Simulink
Avr
Hardware Design
Debugging
Logic Synthesis
Altera Quartus
Uvm
Rtl Design
Synopsys Tools
Icarus Verilog
Computer Architecture
Cache Memory
Cadence Spectre
Cadence Encounter
Cmos
Xilinx Ise 14.7
Xilinx Chipscope Pro
Xilinx Vivado 2014.2
Ovm
Fpga P&R
Vi Editor
Verilog
Embedded Systems
C++
Asic
Hardware Architecture
Systemverilog
Modelsim
Automation
Cadence Virtuoso
Perl Script
Perl
Embedded C
Fpga
Plc
Simulink
Avr
Hardware Design
Debugging
Logic Synthesis
Altera Quartus
Uvm
Rtl Design
Synopsys Tools
Icarus Verilog
Computer Architecture
Cache Memory
Cadence Spectre
Cadence Encounter
Cmos
Xilinx Ise 14.7
Xilinx Chipscope Pro
Xilinx Vivado 2014.2
Ovm
Fpga P&R
Vi Editor
Interests:
Embedded Systems
Cadence Virtuoso
Vlsi
Hardware Design
Synopsis
Cadence Virtuoso
Vlsi
Hardware Design
Synopsis
Languages:
English
Certifications:
Embedded Systems Design and Programming Using Avr Microcontollers
Electronics and Telecommunication Engineering Department of Sardar Patel Institute of Technology, Andheri(W)
Electronics and Telecommunication Engineering Department of Sardar Patel Institute of Technology, Andheri(W)