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Pankaj U Raghuvanshi

from San Jose, CA
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Also known as:
P Raghuvanshi
Phone and address:
5128 Shady Ave, San Jose, CA 95129
Connected to:
Abhishek Raghuvanshi, 43Manish Raghuvanshi, 49Priya Raghuvanshi, 52Geetha Raghuveer, 68Pranav Raghuveer, 36Amit Raghuwanshi, 39Kapil Raghuwanshi, 42Raghvendra S Raghuwanshi, 46Rakesh Raghuwanshi, 47Rohan S Raghuwanshi, 34

Pankaj Raghuvanshi Phones & Addresses

  • 5128 Shady Ave, San Jose, CA 95129
  • 1550 Iron Point Rd, Folsom, CA 95630
  • 901 Brookhill St, Hillsboro, OR 97124

Publications

Us Patents

Technique For Promoting Efficient Instruction Fusion

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US Patent:
20100115248, May 6, 2010
Filed:
Oct 30, 2008
Appl. No.:
12/290395
Inventors:
Ido Ouziel - Zrufa, IL
Lihu Rappoport - Haifa, IL
Robert Valentine - Kiryat Tivon, IL
Ron Gabor - Raanana, IL
Pankaj Raghuvanshi - Hillsboro OR, US
International Classification:
G06F 9/30
US Classification:
712226, 712E09016
Abstract:
A technique to enable efficient instruction fusion within a computer system. In one embodiment, a processor logic delays the processing of a second instruction for a threshold amount of time if a first instruction within an instruction queue is fusible with the second instruction.

Regulating Atomic Memory Operations To Prevent Denial Of Service Attack

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US Patent:
20120072984, Mar 22, 2012
Filed:
Sep 22, 2010
Appl. No.:
12/887898
Inventors:
MICHAEL S. BAIR - Banks OR, US
David W. Burns - Portland OR, US
Robert S. Chappell - Portland OR, US
Prakash Math - Portland OR, US
Leslie A. Ong - Portland OR, US
Pankaj Raghuvanshi - Hillsboro OR, US
Shlomo Raikin - Geva Carmel, IL
Raanan Sade - Kibutz Gvat, IL
Michael D. Tucknott - Hillsboro OR, US
Igor Yanover - Nesher, IL
International Classification:
G06F 21/00
US Classification:
726 22
Abstract:
In one embodiment, the present invention includes a method for identifying a termination sequence for an atomic memory operation executed by a first thread, associating a timer with the first thread, and preventing the first thread from execution of a memory cluster operation after completion of the atomic memory operation until a prevention window has passed. This method may be executed by regulation logic associated with a memory execution unit of a processor, in some embodiments. Other embodiments are described and claimed.

Thermal Management For Extended Reality Ecosystem

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US Patent:
20230112115, Apr 13, 2023
Filed:
Oct 12, 2021
Appl. No.:
17/499757
Inventors:
- Menlo Park CA, US
Eugene Gorbatov - Sammamish WA, US
Pankaj Raghuvanshi - San Jose CA, US
Shrirang Madhav Yardi - San Jose CA, US
International Classification:
G06F 1/20
G06F 1/16
G06T 15/00
Abstract:
A method by a computing system associated with a set of disjoint devices that includes at least one wearable device includes receiving a request to perform a task. The method further includes determining, based on sensor data associated with the set of disjoint devices, a thermal-constraint differential for each device of the set of disjoint devices. The method further includes determining a plurality of workload assignments needed to be performed to accomplish the task. The method further includes distributing, based on the thermal-constraint differentials of the set of disjoint devices, the plurality of workload assignments to one or more devices of the set of disjoint devices to satisfy one or more power or thermal constraints associated with each device of the set of disjoint devices. The method further includes performing the task by causing the one or more devices to execute the distributed plurality of work assignments.

Efficient Instruction Fusion By Fusing Instructions That Fall Within A Counter-Tracked Amount Of Cycles Apart

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US Patent:
20170003965, Jan 5, 2017
Filed:
Apr 30, 2016
Appl. No.:
15/143520
Inventors:
Ido Ouziel - Ein Carmel, IL
Lihu Rappoport - Haifa, IL
Robert Valentine - Kiryat Tivon, IL
Ron Gabor - Hertzliya, IL
Pankaj Raghuvanshi - Hillsboro OR, US
International Classification:
G06F 9/30
G06F 12/0875
Abstract:
A technique to enable efficient instruction fusion within a computer system. In one embodiment, a processor logic delays the processing of a second instruction for a threshold amount of time if a first instruction within an instruction queue is fusible with the second instruction.

Efficient Instruction Fusion By Fusing Instructions That Fall Within A Counter-Tracked Amount Of Cycles Apart

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US Patent:
20160378487, Dec 29, 2016
Filed:
Apr 30, 2016
Appl. No.:
15/143518
Inventors:
Ido Ouziel - Ein Carmel, IL
Lihu Rappoport - Haifa, IL
Robert Valentine - Kiryat Tivon, IL
Ron Gabor - Hertzliya, IL
Pankaj Raghuvanshi - Hillsboro OR, US
International Classification:
G06F 9/30
G06F 12/0875
Abstract:
A technique to enable efficient instruction fusion within a computer system. In one embodiment, a processor logic delays the processing of a second instruction for a threshold amount of time if a first instruction within an instruction queue is fusible with the second instruction.

Efficient Instruction Fusion By Fusing Instructions That Fall Within A Counter-Tracked Amount Of Cycles Apart

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US Patent:
20160246600, Aug 25, 2016
Filed:
Apr 30, 2016
Appl. No.:
15/143522
Inventors:
Ido Ouziel - , US
Lihu Rappoport - Haifa, IL
Robert Valentine - Kiryat Tivon, IL
Ron Gabor - Hertzliya, IL
Pankaj Raghuvanshi - Hillsboro OR, US
International Classification:
G06F 9/30
G06F 13/40
G06F 12/08
Abstract:
A technique to enable efficient instruction fusion within a computer system. In one embodiment, a processor logic delays the processing of a second instruction for a threshold amount of time if a first instruction within an instruction queue is fusible with the second instruction.

Hierarchical Clock Control Using Hysterisis And Threshold Management

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US Patent:
20150362978, Dec 17, 2015
Filed:
Jun 16, 2014
Appl. No.:
14/305514
Inventors:
- Cupertino CA, US
Pradeep Kanapathipillai - Santa Clara CA, US
Chetana N. Keltcher - Lexington MA, US
Pankaj Raghuvanshi - San Jose CA, US
International Classification:
G06F 1/32
Abstract:
In some embodiments, a system may include a sub-hierarchy clock control. In some embodiments, the system may include a master unit. The master unit may include an interface unit electrically coupled to a slave unit. The interface unit may monitor, during use, usage requests of the slave unit by the master unit. In some embodiments, the interface unit may turn off clocks to the slave unit during periods of nonuse. In some embodiments, the interface unit may determine if a predetermined period of time elapses before turning on clocks to the slave unit such that turning off the slave unit resulted in the system achieving greater efficiency. In some embodiments, the interface unit may maintain, during use, power to the slave unit during periods of nonuse. The interface unit may maintain power to the slave unit during periods of nonuse such that data stored in the slave unit is preserved.
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Pankaj U Raghuvanshi from San Jose, CA Get Report