Search

Oscar E Agazzi

from Irvine, CA
Age ~75
Get Report
Connected to:
Edward O Agba, 50Deborah I Agbabi, 38Rashidath B Agbabiaka, 42Rommel M Agbada, 45Bola K Agbaje, 64Oluropo C Agbaje, 47Abram Agban, 33Judy Agbanawag, 78Roger E Agbanawag, 58Diosdado L Agbanlog, 58

Oscar Agazzi Phones & Addresses

  • 38 Deerfield Ave, Irvine, CA 92606 (949) 726-0822
  • 225 Ridgedale Ave, Florham Park, NJ 07932 (973) 301-0843
  • Somerset, NJ
  • Scotch Plains, NJ

Resumes

Resumes

Oscar Agazzi Photo 1

Vice President And Chief Systems Architect

View page
Industry:
Venture Capital & Private Equity
Work:
Broadcom 1996 - 2004
Technical Director
Att 1987 - 1996
Distinguished Member of Technica Staff
Nokia Bell Labs 1987 - 1996
Member of Technical Staff
Clariphy Communications 1987 - 1996
Vice President and Chief Systems Architect
Education:
University of California, Berkeley 1978 - 1982
Oscar Agazzi Photo 2

Oscar Agazzi

View page

Publications

Us Patents

Timing Recovery System For A Multi-Pair Gigabit Transceiver

View page
US Patent:
6363129, Mar 26, 2002
Filed:
Nov 9, 1999
Appl. No.:
09/437721
Inventors:
Oscar E. Agazzi - Irvine CA
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H04L 700
US Classification:
375355, 375371, 331 2, 331 46
Abstract:
A method and a timing recovery system for generating a set of clock signals in a system which includes a set of subsystems. Each of the subsystems includes an analog section. The set of clock signals includes a set of sampling clock signals. Each of the analog sections operates in accordance with a corresponding one of the sampling clock signals. For each of the sampling clock signals, a phase error is generated from a corresponding phase detector. The phase errors are filtered by a set of corresponding loop filters. The filtered phase errors are provided to a set of corresponding oscillators to generate phase control signals. The phase control signals are provided to a set of corresponding phase selectors to generate the sampling clock signals.

Multi-Pair Transceiver Decoder System With Low Computation Slicer

View page
US Patent:
6373900, Apr 16, 2002
Filed:
Jan 22, 2001
Appl. No.:
09/767101
Inventors:
Oscar E. Agazzi - Irvine CA
David Kruse - Newport Beach CA
Arthur Abnous - Irvine CA
Mehdi Hatamian - Viejo CA
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H04L 2534
US Classification:
375288, 375260, 375265
Abstract:
A method and a system for decoding information signals encoded by a multi-state encoding architecture and transmitted over a multi-dimensional transmission channel by computing a distance of a received word from a codeword. One-dimensional (1D) input signals are detected in a symbol decoder, implemented using look-up tables, to produce a pair of 1D errors, with each representing a distance metric between the input signal and a symbol in one of two disjoint symbol-subsets. The symbol decoder is implemented as a pair of slicers, each detecting an input signal with respect to one of two disjoint symbol-subsets. A third slicer detects the input with respect to the union of the two disjoint symbol-subsets. Decisions from the first, second and third slicers are processed to define 1D square error terms expressed in Hamming metrics. Reduced bit count error terms allow follow-on error processing to be performed with a minimum of computational complexity.

Method Of Downsampling Documents

View page
US Patent:
6389178, May 14, 2002
Filed:
Jul 28, 1994
Appl. No.:
08/281879
Inventors:
Oscar Ernesto Agazzi - Florham Park NJ
Kenneth Ward Church - Chatham NJ
William Arthur Gale - Maplewood NJ
Assignee:
Lucent Technologies Inc. - Murray Hill NJ
International Classification:
G06K 936
US Classification:
382276
Abstract:
A method downsamples characters in a document by font substitution when the characters in the document are identified with sufficient reliability. Otherwise, the characters are downsampled by decimation. The method also allows downsampling by applying characters to a two-dimensional nonlinear filter and decimating.

Multi-Pair Gigabit Ethernet Transceiver

View page
US Patent:
6459746, Oct 1, 2002
Filed:
Feb 9, 2001
Appl. No.:
09/781914
Inventors:
Oscar E. Agazzi - Irvine CA
John L. Creigh - Rancho Santa Margarita CA
Mehdi Hatamian - Mission Viejo CA
David E. Kruse - Utrecht, NL
Arthur Abnous - Irvine CA
Henry Samueli - San Juan Capistrano CA
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H04L 700
US Classification:
375371, 370516
Abstract:
Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitters partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals.

Apparatus For, And Method Of, Reducing Noise In A Communications System

View page
US Patent:
6463041, Oct 8, 2002
Filed:
Mar 7, 2001
Appl. No.:
09/801235
Inventors:
Oscar E. Agazzi - Irvine CA
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H04B 320
US Classification:
370286, 379410
Abstract:
A communication line having a plurality of twisted wire pairs connects a plurality of transmitters, one transmitter at each end of each twisted wire pair, with a plurality of receivers, one receiver at each end of each twisted wire pair. Each receiver receives a combination signal including a direct signal from the transmitter at the opposite end of the twisted wire pair with which the receiver is associated and a plurality of far-end crosstalk (FEXT) impairment signals, one from each of the remaining transmitters at the opposite end of the communications line. A plurality of FEXT cancellation systems, one associated with each receiver, provides a replica FEXT impairment signal. A device associated with each receiver is responsive to the combination signal received by the receiver and the replica FEXT impairment signal provided by the FEXT cancellation system associated with the receiver for substantially removing the FEXT impairment signals from the combination signal. If necessary, a skew adjuster delays the arrival of the combination signal at the device so that the combination signal and the FEXT impairment signal arrive at the device at substantially the same time. A sequential decoder operates on signals from each of the plurality of wire pairs simultaneously to produce receiver outputs.

Gigabit Ethernet Transceiver With Analog Front End

View page
US Patent:
6472940, Oct 29, 2002
Filed:
Nov 13, 2000
Appl. No.:
09/712422
Inventors:
Arya R. Behzad - Danville CA
Klaas Bult - Boschen Duin, NL
Ramon A. Gomez - Fountain Valley CA
Chi-Hung Lin - Mission Viejo CA
Tom W. Kwan - Cupertino CA
Oscar E. Agazzi - Irvine CA
John L. Creigh - Rancho Santa CA
Mehdi Hatamian - Mission Viejo CA
David E. Kruse - Bunnik, NL
Arthur Abnous - Irvine CA
Henry Samueli - Corona del Mar CA
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
G03G 310
US Classification:
330279, 330144
Abstract:
Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductors switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.

Dynamic Regulation Of Power Consumption Of A High-Speed Communication System

View page
US Patent:
6477199, Nov 5, 2002
Filed:
Oct 11, 2000
Appl. No.:
09/686513
Inventors:
Oscar E. Agazzi - Irvine CA
John L. Creigh - Rancho Santa Margarita CA
Mehdi Hatamian - Mission Viejo CA
Henry Samueli - San Juan Capistrano CA
Assignee:
Broadcom Corp. - Irvine CA
International Classification:
H03H 730
US Classification:
375232, 375229, 375233, 375350, 708322
Abstract:
A method for dynamically regulating the power consumption of a high-speed integrated circuit which includes a multiplicity of processing blocks. A first metric and a second metric, which are respectively related to a first performance parameter and a second performance parameter of the integrated circuit, are defined. The first metric is set at a pre-defined value. Selected blocks of the multiplicity of processing blocks are disabled in accordance with a set of pre-determined patterns. The second metric is evaluated, while the disabling operation is being performed, to generate a range of values of the second metric. Each of the values corresponds to the pre-defined value of the first metric. A most desirable value of the second metric is determined from the range of values and is matched to a corresponding pre-determined pattern. The integrated circuit is subsequently operated with selected processing blocks disabled in accordance with the matching pre-determined pattern.

Multi-Pair Gigabit Ethernet Transceiver

View page
US Patent:
6477200, Nov 5, 2002
Filed:
Nov 9, 1999
Appl. No.:
09/437719
Inventors:
Oscar E. Agazzi - Irvine CA
John L. Creigh - Rancho Santa Margarita CA
Mehdi Hatamian - Mission Viejo CA
David E. Kruse - Utrecht, NL
Arthur Abnous - Irvine CA
Henry Samueli - San Juan Capistrano CA
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H03H 730
US Classification:
375233, 375285
Abstract:
Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitters partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals.
Control profile
Oscar E Agazzi from Irvine, CA, age ~75 Get Report