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Onur Fidaner Phones & Addresses

  • Covington, LA
  • Houston, TX
  • San Jose, CA
  • Sunnyvale, CA
  • Santa Clara, CA
  • Stanford, CA
  • 3507 Palmilla Dr UNIT 3035, San Jose, CA 95134

Work

Company: Solar junction Dec 2008 Position: Manager of advanced device development

Education

Degree: Doctor of Philosophy (PhD) School / High School: Stanford University 2003 to 2007 Specialities: Electrical Engineering

Skills

Nanotechnology • Matlab • Semiconductors • Optics • Photonics • Solar Cells • Materials Science • Product Development • Management • Technology Integration • Applied Physics • Technical Marketing • Tableau • Multiphysics Modeling • Inverse Problems • Comsol

Languages

English • Turkish

Interests

Consulting • New Technologies

Industries

Medical Devices

Resumes

Resumes

Onur Fidaner Photo 1

Co Founder

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Location:
Houston, TX
Industry:
Medical Devices
Work:
Solar Junction since Dec 2008
Manager of Advanced Device Development

PhotonIC Corp. Oct 2007 - Dec 2008
Sr. Process Engineer

Stanford University 2001 - 2007
Research Assistant
Education:
Stanford University 2003 - 2007
Doctor of Philosophy (PhD), Electrical Engineering
Stanford University 2001 - 2003
Master of Science (M.S.), Electrical Engineering
Middle East Technical University 1997 - 2001
B.S., Electrical Engineering
Skills:
Nanotechnology
Matlab
Semiconductors
Optics
Photonics
Solar Cells
Materials Science
Product Development
Management
Technology Integration
Applied Physics
Technical Marketing
Tableau
Multiphysics Modeling
Inverse Problems
Comsol
Interests:
Consulting
New Technologies
Languages:
English
Turkish

Publications

Us Patents

Wafer-Level Quasi-Planarization And Passivation For Multi-Height Structures

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US Patent:
20040253808, Dec 16, 2004
Filed:
Jun 14, 2003
Appl. No.:
10/460880
Inventors:
Hilmi Demir - Stanford CA, US
Onur Fidaner - Stanford CA, US
David Andrew Miller - Stanford CA, US
Vijit Sabnis - Menlo Park CA, US
International Classification:
H01L021/44
H01L021/4763
US Classification:
438/631000, 438/597000, 438/669000, 438/944000, 438/633000
Abstract:
Methods in accordance with the present invention provide a quasi-planarized surface between one or more semiconductor devices and at least a portion of surrounding passivation material, where the devices have different elevations above a substrate. A hard mask defines the planarized surface as the interface between the hard mask and both the passivation layer and the device, after a passivation layer etching process. The resulting planarized surface has a small to zero step height, is insensitive to passivation layer non-uniformity and etch non-uniformity, provides full passivation of the device side wall, provides protection for the device against etch-induced damage, and prevents the detrimental effects of passivation layer voids. The methods are applicable to semiconductor device fabrication for electronic and photonic/optoelectronic systems such as, but not limited to, cell phones, networking systems, high brightness (HB) LEDs, laser diodes (LDs), photodiodes, modulator diodes and multifunction solar cells.

Method For Making Semiconductor Light Detection Devices

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US Patent:
20130105930, May 2, 2013
Filed:
Oct 27, 2011
Appl. No.:
13/283379
Inventors:
Lan Zhang - Palo Alto CA, US
Ewelina N. Lucow - Mountain View CA, US
Onur Fidaner - Sunnyvale CA, US
Michael W. Wiemer - Campbell CA, US
Assignee:
Solar Junction Corporation - San Jose CA
International Classification:
H01L 31/18
H01L 31/0216
US Classification:
257437, 438 72, 257E31119
Abstract:
A semiconductor light detection device fabrication technique is provided in which the cap etch and anti-reflection coating steps are performed in a single, self-aligned lithography module.
Onur Fidaner from Covington, LA, age ~45 Get Report