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Omid J Azizi

from Emerald Hills, CA
Age ~42
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Connected to:
Aman Azizi, 65Aris Azizi, 32Dina F Azizi, 60Ehsan Azizi, 41Elham Azizi, 39Frank Azizi, 62Hamed K Azizi, 64Hussein Azizi, 47Jessica S Azizi, 39John M Azizi, 98

Omid Azizi Phones & Addresses

  • 715 Windsor Way, Redwood City, CA 94061
  • Emerald Hills, CA
  • Stanford, CA
  • 137 Running Farm Ln APT 101, Stanford, CA 94305

Publications

Us Patents

Hardware-Assisted Paging Mechanisms

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US Patent:
20200004677, Jan 2, 2020
Filed:
Jun 27, 2018
Appl. No.:
16/020444
Inventors:
- Santa Clara CA, US
Omid Azizi - Redwood City CA, US
Chandan Egbert - San Jose CA, US
David Hansen - Santa Clara CA, US
Andreas Kleen - Portland OR, US
Mahesh Maddury - Santa Clara CA, US
Mahesh Madhav - Portland OR, US
Alexandre Solomatnikov - San Carlos CA, US
John Peter Stevenson - Chicago IL, US
International Classification:
G06F 12/02
G06F 12/1009
G06F 3/06
Abstract:
Processing circuitry for computer memory management includes memory reduction circuitry to implement a memory reduction technique; and reference count information collection circuitry to: access a memory region, the memory region subject to the memory reduction technique; obtain an indication of memory reduction of the memory region; calculate metrics based on the indication of memory reduction of cache lines associated with the memory region; and provide the metrics to a system software component for use in memory management mechanisms.

Physical Page Tracking For Handling Overcommitted Memory

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US Patent:
20190354487, Nov 21, 2019
Filed:
May 15, 2018
Appl. No.:
15/980523
Inventors:
Amin Firoozshahian - Mountain View CA, US
Mahesh Madhav - Portland OR, US
Toby Opferman - Beaverton OR, US
Omid Azizi - Redwood City CA, US
International Classification:
G06F 12/1009
Abstract:
A system for computer memory management that implements a memory pool table, the memory pool table including entries that describe a plurality of memory pools, each memory pool representing a group of memory pages related by common attributes; a per-page tracking table, each entry in the per-page tracking table used to related a memory page with a memory pool of the memory pool table; and processing circuitry to: scan each entry in the per-page tracking table and, for each entry: determine an amount of memory released if the memory page related with the entry is swapped; aggregate the amount of memory for the respective memory pool related with the memory page related with the entry in the per-page tracking table, to produce a per-pool memory aggregate; and output the per-pool memory aggregate for the memory pools related with the memory pages in the per-page tracking table.

Survivability Guarantees For Memory Traffic

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US Patent:
20190303281, Oct 3, 2019
Filed:
Mar 30, 2018
Appl. No.:
15/941468
Inventors:
Amin Firoozshahian - Mountain View CA, US
Andreas Kleen - Portland OR, US
Stephen Van Doren - Portland OR, US
Omid Azizi - Redwood City CA, US
Mahesh Madhav - Portland OR, US
Mahesh Maddury - Santa Clara CA, US
Chandan Egbert - San Jose CA, US
International Classification:
G06F 12/02
G06F 12/06
Abstract:
Various systems and methods for controlling memory traffic flow rate are described herein. A system for computer memory management, the system comprising: rate control circuitry to: receive a rate exceeded signal from monitoring circuitry, the rate exceeded signal indicating that memory traffic flow from a traffic source exceeds a threshold; receive a distress signal from a memory controller that interfaces with a memory device, the distress signal indicating that the memory device is oversubscribed; and implement throttle circuitry to throttle the memory traffic flow from the traffic source when the rate exceeded signal and the distress signal are both asserted.

Lazy Memory Deduplication

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US Patent:
20190212935, Jul 11, 2019
Filed:
Jan 11, 2018
Appl. No.:
15/868787
Inventors:
Chandan Egbert - Santa Clara CA, US
Amin Firoozshahian - Mountain View CA, US
Mahesh Maddury - Santa Clara CA, US
John Stevenson - Palo Alto CA, US
Henk Neefs - Palo Alto CA, US
Omid Azizi - Redwood City CA, US
International Classification:
G06F 3/06
G06F 12/02
G06F 12/0811
G06F 12/084
G06F 12/0868
Abstract:
Various systems and methods for computer memory management are described herein. A system for computer memory management includes a first memory device including a mapping table; a second memory device including a staging area; a third memory device including a dedup data region; and a controller operable to: receive a memory access request, the memory access request including an address and data; write the data to the staging area; and update the mapping table with the address.

Reservation Architecture For Overcommitted Memory

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US Patent:
20190213120, Jul 11, 2019
Filed:
Jan 11, 2018
Appl. No.:
15/868819
Inventors:
Omid Azizi - Redwood City CA, US
Amin Firoozshahian - Mountain View CA, US
Andreas Kleen - Portland OR, US
Mahesh Madhav - Portland OR, US
Mahesh Maddury - Santa Clara CA, US
Chandan Egbert - San Jose CA, US
Eric Gouldey - Fort Collins CO, US
International Classification:
G06F 12/02
G06F 9/50
G06F 3/06
Abstract:
Various systems and methods for computer memory overcommitment management are described herein. A system for computer memory management includes a memory device to store data and a mapping table; and a memory overcommitment circuitry to: receive a signal to move data in a first block from a memory reduction area in the memory device to a non-memory reduction area in the memory device, the memory reduction area to store data using a memory reduction technique, and the non-memory reduction area to store data without any memory reduction techniques; allocate a second block in the non-memory reduction area; copy the data in the first block to the second block; and update the mapping table to revise a pointer to point to the second block, the mapping table used to store pointers to memory device in the memory reduction area and the non-memory reduction area.

Memory Pressure Notifier

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US Patent:
20190196988, Jun 27, 2019
Filed:
Dec 27, 2017
Appl. No.:
15/855798
Inventors:
- Santa Clara CA, US
Omid Azizi - Redwood City CA, US
Chandan Egbert - San Jose CA, US
Amin Firoozshahian - Mountain View CA, US
David Christopher Hansen - Portland OR, US
Andreas Kleen - Portland OR, US
Mahesh Maddury - Santa Clara CA, US
Mahesh Madhav - Portland OR, US
Ashok Raj - Portland OR, US
Alexandre Solomatnikov - San Carlos CA, US
Stephen Van Doren - Portland OR, US
International Classification:
G06F 13/16
G06F 3/06
Abstract:
Various systems and methods for computer memory management are described herein. A system includes a memory controller to: monitor utilization of a memory device, the memory device used with a memory compression technique; determine that the utilization of the memory device violates a threshold; and initiate a system interrupt to provoke a response, responsive to the utilization of the memory device violating the threshold.

Matrix Multiplication Acceleration Of Sparse Matrices Using Column Folding And Squeezing

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US Patent:
20190042237, Feb 7, 2019
Filed:
Jun 22, 2018
Appl. No.:
16/016278
Inventors:
Omid AZIZI - Redwood City CA, US
Guy BOUDOUKH - Ramat Hasharon, IL
Tony WERNER - Los Altos CA, US
Andrew YANG - Cupertino CA, US
Michael ROTZIN - Santa Clara CA, US
Chen KOREN - Hadera, IL
Eriko NURVITADHI - Hillsboro OR, US
International Classification:
G06F 9/30
G06F 17/16
G06F 9/38
Abstract:
Disclosed embodiments relate to sparse matrix multiplication (SMM) acceleration using column folding and squeezing. In one example, a processor, in response to a SMM instruction having fields to specify locations of first, second, and output matrices, the second matrix being a sparse matrix, uses execution circuitry to pack the second matrix by replacing one or more zero-valued elements with non-zero elements yet to be processed, each of the replaced elements further including a field to identify its logical position within the second matrix, and, the execution circuitry further to, for each non-zero element at row M and column K of the specified first matrix, generate a product of the element and each corresponding non-zero element at row K, column N of the packed second matrix, and accumulate each generated product with a previous value of a corresponding element at row M and column N of the specified output matrix.

Pause Communication From I/O Devices Supporting Page Faults

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US Patent:
20190042461, Feb 7, 2019
Filed:
Apr 20, 2018
Appl. No.:
15/958591
Inventors:
Rupin Vakharwala - Hillsboro OR, US
Amin Firoozshahian - Mountain View CA, US
Stephen Van Doren - Portland OR, US
Rajesh Sankaran - Portland OR, US
Mahesh Madhav - Portland OR, US
Omid Azizi - Redwood City CA, US
Andreas Kleen - Portland OR, US
Mahesh Maddury - Santa Clara CA, US
Ashok Raj - Portland OR, US
International Classification:
G06F 12/1009
G06F 3/06
G06F 12/0862
G06F 9/38
Abstract:
A processing device includes a core to execute instructions, and memory management circuitry coupled to, memory, the core and an I/O device that supports page faults. The memory management circuitry includes an express invalidations circuitry, and a page translation permission circuitry. The memory management circuitry is to, while the core is executing the instructions, receive a command to pause communication between the I/O device and the memory. In response to receiving the command to pause the communication, modify permissions of page translations by the page translation permission circuitry and transmit an invalidation request, by the express invalidations circuitry to the I/O device, to cause cached page translations in the I/O device to be invalidated.
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Omid J Azizi from Emerald Hills, CA, age ~42 Get Report