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Oleg V Korobeynikov

from Hillsboro, OR
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Also known as:
O Korobeynikov
Connected to:
Alicia B Korobij, 45Andrew T Korobkin, 34Bryan D Korobkin, 43Artem A Korobko, 34Yuriy Korobko, 77Alexander Korobov, 50Alexey Korobov, 35Thomas A Korocz, 56Cameron G Korody, 27Melanie A Koroghlian, 53

Oleg Korobeynikov Phones & Addresses

  • Hillsboro, OR
  • 700 Franklin St, Melrose, MA 02176 (781) 665-8280 (781) 665-0170
  • 1008 Paradise Rd, Swampscott, MA 01907 (781) 599-6407
  • 1008 Paradise Rd #2M, Swampscott, MA 01907 (781) 599-6407
  • 353 NE Autumn Rose Way APT F, Hillsboro, OR 97124 (781) 599-6407

Work

Position: Clerical/White Collar

Education

Degree: High school graduate or higher

Publications

Us Patents

Methods And Apparatus For Analog-Digital Signal Conversion

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US Patent:
20080158031, Jul 3, 2008
Filed:
Dec 20, 2007
Appl. No.:
11/961960
Inventors:
Joseph M. Kulinets - North Andover MA, US
Peter R. Nuytkens - Melrose MA, US
Oleg V. Korobeynikov - Swampscott MA, US
Assignee:
Custom One Design, Inc. - Melrose MA
International Classification:
H03M 3/00
H03M 1/38
US Classification:
341143, 341161
Abstract:
Methods and apparatus for the conversion of analog signals into digital signals using second order or higher sigma-delta modulators in pipelined or cyclic architectures.

Apparatus For Current-To-Voltage Integration For Current-To-Digital Converter

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US Patent:
20090273386, Nov 5, 2009
Filed:
May 1, 2008
Appl. No.:
12/113728
Inventors:
Oleg Korobeynikov - Swampscott MA, US
Joseph M. Kulinets - North Andover MA, US
Vladimir Protasov - Revere MA, US
Peter R. Nuytkens - Melrose MA, US
Assignee:
Custom One Design, Inc - Melrose MA
International Classification:
G06G 7/186
US Classification:
327337
Abstract:
Methods and apparatus for improved current-to-voltage integrators reducing charge injection and kT/C errors from capacitor switching and intrinsic operational amplifier noise (i.e., offset, 1/f noise, thermal noise) during the reset cycle of the integrator, simultaneously reducing demands on the reference voltage source, using correlated double sampling to compensate for DC offset and low frequency op-amp noises, and “fake” integration and a capacitor divider to eliminate or significantly reduce kT/C noise and charge injection.

Methods And Apparatus For Reducing Non-Ideal Effects In Correlated Double Sampling Compensated Circuits

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US Patent:
20090273392, Nov 5, 2009
Filed:
May 1, 2008
Appl. No.:
12/113731
Inventors:
Oleg Korobeynikov - Swampscott MA, US
Joseph M. Kulinets - North Andover MA, US
Vladimir Protasov - Revere MA, US
Peter R. Nuytkens - Melrose MA, US
Assignee:
Custom One Design, Inc. - Meelrose MA
International Classification:
H03K 5/00
US Classification:
327551
Abstract:
Embodiments of the present invention address kT/C noise, sampled high frequency operational amplifier noise, and charge injection errors sampled on switching capacitors and introduced due to internal switching. Correlated double sampling compensates for DC offset and low frequency operational amplifier noise, and the use of fake integration and a capacitor divider eliminate or significantly reduce kT/C noise, sampled high frequency operational amplifier noise, and charge injection errors.
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Oleg V Korobeynikov from Hillsboro, OR Get Report